| Patent application number | Description | Published |
|---|
| 20090106555 | System and Method For Control Of Security Configurations - Systems and methods are disclosed for using cryptographic techniques to configure data processing systems. A configuration manager cryptographically controls the configuration of a system by ensuring that only authorized users or applications can change the configuration. For example, requests to change configuration information may include authenticated and/or encrypted data. These cryptographic techniques are employed to enable and/or disable functions, features and capabilities of a system. For example, a system may be reconfigured to provide strong or weak encryption based on parameters in the configuration information. | 04-23-2009 |
| 20090319775 | Data Path Security Processing - Methods and associated systems provide secured data transmission over a data network. A security device provides security processing in the data path of a packet network. The device may include at least one network interface to send packets to and receive packets from a data network and at least one cryptographic engine for performing encryption, decryption and/or authentication operations. The device may be configured as an in-line security processor that processes packets that pass through the device as the packets are routed to/from the data network. | 12-24-2009 |
| 20090323931 | Data Processing Hash Algorithm and Policy Management - Methods and associated systems for processing data are disclosed. A hashing function sequentially processes a hash key to generate a hash value. A policy management system processes packets according to defined policies. | 12-31-2009 |
| 20100235647 | Hardware Security for Software Processes - A system and method for secure processing is provided, wherein a monitor application is injected into a secure application binary within the security perimeter of a secure processor. The components of the monitor application are injected into different portions of the application binary utilizing a seed value. In this manner, the positioning of the monitor application in the application binary is altered each time the application binary is booted. After the monitor application is inserted into the application binary, the secure process is passed to the host processor for execution. During execution of the secure process, a system and method is provided for the monitor application to communicate, to the secure processor, attempts to tamper with or attack the secure process. | 09-16-2010 |
| 20100290624 | Key Management System and Method - Methods and systems are disclosed for providing secured data transmission and for managing cryptographic keys. One embodiment of the invention provides secure key management when separate devices are used for generating and utilizing the keys. One embodiment of the invention provides secure storage of keys stored in an unsecured database. One embodiment of the invention provides key security in conjunction with high speed decryption and encryption, without degrading the performance of the data network. | 11-18-2010 |
| Patent application number | Description | Published |
|---|
| 20080247242 | Method Using a One-Time Programmable Memory Cell - A one-time programmable device includes a controller, a protection system, a static storage element and a latch, which can be referred to as a latch-based one-time programmable (OTP) element. In one example, the static storage element includes a thin gate-oxide that acts as a resistance element, which, depending on whether its blown, sets the latch into one of two states. | 10-09-2008 |
| 20090109723 | Quad SRAM Based One Time Programmable Memory - A quad SRAM based one time programmable memory cell is provided. Prior to programming, the memory cell operates as an SRAM memory cell. After programming, the memory cell operates as a one-time programmable non-volatile memory cell. The memory cell includes a storage element coupled at a first side to a first upper fuse and a first lower fuse and coupled at a second side to a second upper fuse and a second lower fuse. When the first upper fuse and second lower fuse are programmed, the storage element outputs a first value. When the second upper fuse and first lower fuse are programmed, the storage element outputs a second value. After programming the upper fuse acts as a pull-up fuse and the lower fuse acts as a pull-down fuse hold the state of the cell. | 04-30-2009 |
| 20090109724 | Differential Latch-Based One Time Programmable Memory - A differential latch-based one time programmable memory cell is provided. The differential latch-based one time programmable memory cell includes a differential latching amplifier having a first set of fuse devices coupled to the first input and a second set of fuse devices coupled to the second input. Only one set of fuse devices can be programmed in a memory cell. If one or more fuse devices in a set of fuse devices are programmed, the side having the programmed fuse will present a lower voltage at its input to the differential latching amplifier. Differential latching amplifier outputs a “0” or a “1” depending on the side having the programmed fuse. | 04-30-2009 |
| 20090237974 | Programmable memory cell - A disclosed embodiment is a programmable memory cell comprising an elevated ground node having a voltage greater than a common ground node by an amount substantially equal to a voltage drop across a trigger point adjustment element. In one embodiment, the trigger point adjustment element can be a diode. The trigger voltage of the programmable memory cell is raised closer to a supply voltage when current passes through the trigger point adjustment element during a write operation. The programmable memory cell can comprise a pair of cross-coupled inverters, and first and second programmable antifuses that can be coupled to each inverter in the pair of cross-coupled inverters. Since the trigger voltage of the programmable memory cell is raised closer to the supply voltage, a programmed antifuse can easily reach below the trigger voltage and result in a successful write operation even when the supply voltage is a low voltage. | 09-24-2009 |
| 20100014340 | Quad SRAM Based One Time Programmable Memory - A differential latch-based one time programmable memory cell is provided. The differential latch-based one time programmable memory cell includes a differential latching amplifier having a first set of fuse devices coupled to the first input and a second set of fuse devices coupled to the second input. Only one set of fuse devices can be programmed in a memory cell. If one or more fuse devices in a set of fuse devices are programmed, the side having the programmed fuse will present a lower voltage at its input to the differential latching amplifier. Differential latching amplifier outputs a “0” or a “1” depending on the side having the programmed fuse. | 01-21-2010 |
| 20100118584 | MEMORY DEVICE USING ANTIFUSES - Herein described is a method of implementing one or more native NMOS antifuses in an integrated circuit. Also described is a method for programming one or more native NMOS antifuses used within a memory device. The method further comprises verifying one or more states of the one or more native NMOS antifuses after the programming has been performed. In a representative embodiment, the one or more native NMOS antifuses are implemented by blocking the implantation of a dopant into a substrate of an integrated circuit. In a representative embodiment, an integrated circuit incorporates the use of one or more native NMOS antifuses. In a representative embodiment, the integrated circuit comprises a memory device, such as a one time programmable memory. | 05-13-2010 |
| 20100177581 | Very Small Swing High Performance Asynchronous CMOS Static Memory (Multi-Port Register File) With Power Reducing Column Multiplexing Scheme - The present invention relates to a multi-port register file memory or SRAM including a plurality of storage elements and other circuitry that operate synchronously or asynchronously. The storage elements are arranged in rows and columns and store data. Two read port pairs are coupled to each of the storage elements and a differential sensing device or circuit. The read port is coupled to the storage elements in an isolated manner, enabling a plurality of cells to be arranged in such rows and columns. The sensing device is adapted to sense a small voltage swing. A column mux circuit is coupled to each column and the sensing device. Performance is not degraded unusually as the power supply voltage is reduced due to bus drop or inductive effects. | 07-15-2010 |
