| Patent application number | Description | Published |
|---|
| 20100102386 | Lateral double-diffused metal oxide semiconductor (LDMOS) transistors - Methods of making, structures, devices, and/or applications for lateral double-diffused metal oxide semiconductor (LDMOS) transistors are disclosed. In one embodiment, an LDMOS transistor can include: (i) an n-doped deep n-well (DNW) region on a substrate; (ii) a gate oxide and a drain oxide between a source region and a drain region of the LDMOS transistor, the gate oxide being adjacent to the source region, the drain oxide being adjacent to the drain region; (iii) a conductive gate over the gate oxide and a portion of the drain oxide; (iv) a p-doped p-body region in the source region; (v) an n-doped drain region in the drain region; (vi) a first n-doped n+ region and a p-doped p+ region adjacent thereto in the p-doped p-body region of the source region; and (vii) a second n-doped n+ region in the drain region. | 04-29-2010 |
| 20100173458 | LATERAL DOUBLE DIFFUSED MOSFET TRANSISTOR WITH A LIGHTLY DOPED SOURCE - Methods and systems for monolithically fabricating a lateral double-diffused MOSFET (LDMOS) transistor having a source, drain, and a gate on a substrate, with a process flow that is compatible with a CMOS process flow are described. | 07-08-2010 |
| 20100301413 | Fabrication of lateral double-diffused metal oxide semiconductor (LDMOS) devices - Methods of making, structures, devices, and/or applications for lateral double-diffused metal oxide semiconductor (LDMOS) transistors are disclosed. In one embodiment, a method of fabricating an LDMOS transistor with source, drain, and gate regions on a substrate, can include: forming p-type and n-type buried layer (PBL, NBL) regions; growing an epitaxial (N-EPI) layer on the NBL/PBL regions; forming a p-doped deep p-well (DPW) region on the PBL region; forming a well region in the N-EPI layer; forming a doped body region; after the doped body region formation, forming an active area and a field oxide (FOX) region, and forming a drain oxide between the source and drain regions of the LDMOS transistor; after the doped body region formation, forming a gate oxide adjacent to the source and drain regions, and forming a gate on the gate oxide and a portion of the drain oxide; and forming a doped drain region, and first and second doped source regions. | 12-02-2010 |
| 20110031947 | Flip chip package for monolithic switching regulator - Methods and apparatuses related to packaging a monolithic voltage regulator are disclosed. In one embodiment, an apparatus includes: (i) a monolithic voltage regulator with a transistor arranged as parallel transistor devices; (ii) bumps on the monolithic voltage regulator to form connections to source and drain terminals of the transistor; (iii) a single layer lead frame with a plurality of interleaving lead fingers coupled to the monolithic voltage regulator via the bumps, where the single layer lead frame includes first and second surfaces, where the first surface includes a first pattern to form connections to the bumps, and where the second surface includes a second pattern that is different from the first pattern; and (iv) a flip-chip package encapsulating the monolithic voltage regulator, the bumps, and the single layer lead frame, where the flip-chip package has external connectors of the monolithic voltage regulator at the second surface of the single layer lead frame. | 02-10-2011 |
| 20110133274 | LATERAL DOUBLE-DIFFUSED MOSFET - A LDMOS transistor is implemented in a first impurity region on a substrate. The LDMOS transistor has a source that includes a second impurity region. The second impurity region is implanted into the surface of the substrate within the first impurity region. Additionally, the LDMOS transistor has a drain that includes a third impurity region. The third impurity region is implanted into the surface of the substrate within the first impurity region. The third impurity region is spaced a predetermined distance away from a gate of the LDMOS transistor. The drain of the LDMOS transistor further includes a fourth impurity region within the third impurity region. The fourth impurity region provides an ohmic contact for the drain. | 06-09-2011 |
| 20110269286 | HEAVILY DOPED REGION IN DOUBLE-DIFFUSED SOURCE MOSFET (LDMOS) TRANSISTOR AND A METHOD OF FABRICATING THE SAME - A transistor includes a source, a drain and a gate. The source includes a p-doped p-body, a p+ region overlapping the p-body, an n+ region overlapping the p-body in proximity to the p+ region, and an n-doped source, heavily double-diffused (SHDD) region, only into the source region of the transistor, the SHDD region having a depth about equal to that of the first n+ region and overlapping the first n+ region. The drain includes a second n+ region and an n-doped shallow drain overlapping the second n+ region. The gate includes a gate oxide and a conductive material over the gate oxide. The SHDD region extends further laterally than the first n+ region beneath the gate oxide. The SHDD region is implanted using a dopant concentration greater than that of the n-doped shallow drain but less than that of the first n+ region. | 11-03-2011 |
