Patent application number | Description | Published |
20130172365 | ARYLOSULFONAMIDES FOR THE TREATMENT OF CNS DISEASES - Arylsulphonamide derivatives of formula (I) and pharmaceutically acceptable salts thereof. The compounds may be useful for the treatment and/or prevention of disorders of the central nervous system. | 07-04-2013 |
20140121216 | INDOLEAMINE DERIVATIVES FOR THE TREATMENT OF CENTRAL NERVOUS SYSTEM DISEASES - Indoleamine derivatives of formula (IA), R | 05-01-2014 |
20140135310 | SULPHONAMIDE DERIVATIVES OF ALICYCLIC AMINES FOR THE TREATMENT OF CENTRAL NERVOUS SYSTEM DISEASES - Sulphonamide derivatives of alicyclic amines of formula (I), wherein A represents naphthyl or 9- or 10-membered bicyclic group, consisting of benzene ring fused with 5- or 6-membered heterocyclic ring; D represents phenyl, naphthyl, 5-membered aromatic heterocyclic group, bicyclic group consisting of a ring selected from benzene and pyridine, fused with aromatic or non-aromatic 5-membered heterocyclic ring; p, r independently represent 0 or 1; x, z independently represent 1 or 2; n is 2 or 3; | 05-15-2014 |
20140336200 | ARYLOSULFONAMIDES FOR THE TREATMENT OF CNS DISEASES - Arylsulphonamide derivatives of formula (I) and pharmaceutically acceptable salts thereof. The compounds may be useful for the treatment and/or prevention of disorders of the central nervous system. | 11-13-2014 |
20150051257 | SULPHONAMIDE DERIVATIVES OF BENZYLAMINE FOR THE TREATMENT OF CNS DISEASES - Sulphonamide derivatives of benzylamine of formula (I), wherein A represents phenyl unsubstituted or substituted; or 9- or 10-membered bicyclic group, linked to —(O) | 02-19-2015 |
Patent application number | Description | Published |
20080283995 | COMPACT MULTI-PORT CAM CELL IMPLEMENTED IN 3D VERTICAL INTEGRATION - A multi-ported CAM cell in which the negative effects of increased travel distance have been substantially reduced is provided. The multi-ported CAM cell is achieved in the present invention by utilizing three-dimensional integration in which multiple active circuit layers are vertically stack and vertically aligned interconnects are employed to connect a device from one of the stacked layers to another device in another stack layer. By vertically stacking multiple active circuit layers with vertically aligned interconnects, each compare port of the multi-port CAM can be implemented on a separate layer above or below the primary data storage cell. This allows the multi-port CAM structure to be implemented within the same area footprint as a standard Random Access Memory (RAM) cell, minimizing data access and match compare delays. Each compare match line and data bit line has the length associated with a simple two-dimensional Static Random Access Memory (SRAM) cell array. | 11-20-2008 |
20080288720 | MULTI-WAFER 3D CAM CELL - A multi-wafer CAM cell in which the negative effects of increased travel distance have been substantially reduced is provided. The multi-wafer CAM cell is achieved in the present invention by utilizing three-dimensional integration in which multiple active circuit layers are vertically stack and vertically aligned interconnects are employed to connect a device from one of the stacked layers to another device in another stack layer. By vertically stacking multiple active circuit layers with vertically aligned interconnects, each compare port of the inventive CAM cell can be implemented on a separate layer above or below the primary data storage cell. This allows the multi-wafer CAM structure to be implemented within the same area footprint as a standard Random Access Memory (RAM) cell, minimizing data access and match compare delays. | 11-20-2008 |
20080291767 | MULTIPLE WAFER LEVEL MULTIPLE PORT REGISTER FILE CELL - A multi-port register file (e.g., memory element) is provided in which each read port of the register file is located in a separate wafer above and/or below the primary data storage element. This is achieved in the present invention by utilizing three-dimensional integration in which multiple active circuit layers are vertically stacked and vertically aligned interconnects are employed to connect a device from one of the stacked layers to another device in another stacked layer. | 11-27-2008 |
20090305462 | COMPACT MULTI-PORT CAM CELL IMPLEMENTED IN 3D VERTICAL INTEGRATION - A multi-ported CAM cell in which the negative effects of increased travel distance have been substantially reduced is provided. The multi-ported CAM cell is achieved in the present invention by utilizing three-dimensional integration in which multiple active circuit layers are vertically stack and vertically aligned interconnects are employed to connect a device from one of the stacked layers to another device in another stack layer. By vertically stacking multiple active circuit layers with vertically aligned interconnects, each compare port of the multi-port CAM can be implemented on a separate layer above or below the primary data storage cell. This allows the multi-port CAM structure to be implemented within the same area footprint as a standard Random Access Memory (RAM) cell, minimizing data access and match compare delays. Each compare match line and data bit line has the length associated with a simple two-dimensional Static Random Access Memory (SRAM) cell array. | 12-10-2009 |
20120127771 | MULTI-WAFER 3D CAM CELL - A multi-wafer CAM cell in which the negative effects of increased travel distance have been substantially reduced is provided. The multi-wafer CAM cell is achieved in the present invention by utilizing three-dimensional integration in which multiple active circuit layers are vertically stack and vertically aligned interconnects are employed to connect a device from one of the stacked layers to another device in another stack layer. By vertically stacking multiple active circuit layers with vertically aligned interconnects, each compare port of the inventive CAM cell can be implemented on a separate layer above or below the primary data storage cell. This allows the multi-wafer CAM structure to be implemented within the same area footprint as a standard Random Access Memory (RAM) cell, minimizing data access and match compare delays. | 05-24-2012 |
Patent application number | Description | Published |
20140181761 | IDENTIFYING CIRCUIT ELEMENTS FOR SELECTIVE INCLUSION IN SPEED-PUSH PROCESSING IN AN INTEGRATED CIRCUIT, AND RELATED CIRCUIT SYSTEMS, APPARATUS, AND COMPUTER-READABLE MEDIA - Embodiments of the disclosure include identifying circuit elements for selective inclusion in speed-push processing and related circuit systems, apparatus, and computer-readable media. A method for altering a speed-push mask is provided, including analyzing a circuit design comprising a plurality of cells to which a speed-push mask is applied to identify at least one of the plurality of cells as having performance margin. The speed-push mask is altered such that the at least one of the plurality of cells having performance margin may be fabricated as a non-speed-pushed cell. Additionally, a method for creating a speed-push mask is provided, including analyzing a circuit design comprising a plurality of cells to identify at least one of the plurality of cells below a performance threshold. A speed-push mask is created such that the at least one of the plurality of cells below the performance threshold may be fabricated as a speed-pushed cell. | 06-26-2014 |
20140367760 | METHOD AND APPARATUS FOR A DIFFUSION BRIDGED CELL LIBRARY - A library of cells for designing an integrated circuit, the library comprises continuous diffusion compatible (CDC) cells. A CDC cell includes a p-doped diffusion region electrically connected to a supply rail and continuous from the left edge to the right edge of the CDC cell; a first polysilicon gate disposed above the p-doped diffusion region and electrically connected to the p-doped diffusion region; an n-doped diffusion region electrically connected to a ground rail and continuous from the left edge to the right edge; a second polysilicon gate disposed above the n-doped diffusion region and electrically connected to the n-doped diffusion region; a left floating polysilicon gate disposed over the p-doped and n-doped diffusion regions and proximal to the left edge; and a right floating polysilicon gate disposed over the p-doped and n-doped diffusion regions and proximal to the right edge. | 12-18-2014 |
20150064864 | METHOD AND APPARATUS FOR A DIFFUSION BRIDGED CELL LIBRARY - A library of cells for designing an integrated circuit, the library comprises continuous diffusion compatible (CDC) cells. A CDC cell includes a p-doped diffusion region electrically connected to a supply rail and continuous from the left edge to the right edge of the CDC cell; a first polysilicon gate disposed above the p-doped diffusion region and electrically connected to the p-doped diffusion region; an n-doped diffusion region electrically connected to a ground rail and continuous from the left edge to the right edge; a second polysilicon gate disposed above the n-doped diffusion region and electrically connected to the n-doped diffusion region; a left floating polysilicon gate disposed over the p-doped and n-doped diffusion regions and proximal to the left edge; and a right floating polysilicon gate disposed over the p-doped and n-doped diffusion regions and proximal to the right edge. | 03-05-2015 |