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Buchwalter, NY

Leena P. Buchwalter, Hopewell Junction, NY US

Patent application numberDescriptionPublished
20090032920LASER RELEASE PROCESS FOR VERY THIN SI-CARRIER BUILD - A laser release and glass chip removal process for a integrated circuit module avoiding carrier edge cracking is provided.02-05-2009
20090032962CENTRIFUGAL METHOD FOR FILING HIGH ASPECT RATIO BLIND MICRO VIAS WITH POWDERED MATERIALS FOR CIRCUIT FORMATION - The present disclosure relates generally to semiconductor, integrated circuits, and particularly, but not by way of limitation, to centrifugal methods of filling high-aspect ratio vias and trenches with powders, pastes, suspensions of materials to act as any of a conducting, structural support, or protective member of an electronic component.02-05-2009

Patent applications by Leena P. Buchwalter, Hopewell Junction, NY US

Leena Paivikki Buchwalter, Hopewell Junction, NY US

Patent application numberDescriptionPublished
20080217778METHOD TO CREATE FLEXIBLE CONNECTIONS FOR INTEGRATED CIRCUITS - A method of producing flexible interconnections for integrated circuits, and, in particular, the forming of flexible or compliant interconnections preferably by a laser-assisted chemical vapor deposition process in semiconductor or glass substrate-based carriers which are employed for mounting and packaging multiple integrated circuit chips and selectively, other devices in the technology.09-11-2008
20090108381Low temperature bi-CMOS compatible process for MEMS RF resonators and filters - A method of formation of a microelectromechanical system (MEMS) resonator or filter which is compatible with integration with any analog, digital, or mixed-signal integrated circuit (IC) process, after or concurrently with the formation of the metal interconnect layers in those processes, by virtue of its materials of composition, processing steps, and temperature of fabrication is presented. The MEMS resonator or filter incorporates a lower metal level, which forms the electrodes of the MEMS resonator or filter, that may be shared with any or none of the existing metal interconnect levels on the IC. It further incorporates a resonating member that is comprised of at least one metal layer for electrical connection and electrostatic actuation, and at least one dielectric layer for structural purposes. The gap between the electrodes and the resonating member is created by the deposition and subsequent removal of a sacrificial layer comprised of a carbon-based material. The method of removal of the sacrificial material is by an oxygen plasma or an anneal in an oxygen containing ambient. A method of vacuum encapsulation of the MEMS resonator or filter is provided through means of a cavity containing the MEMS device, filled with additional sacrificial material, and sealed. Access vias are created through the membrane sealing the cavity; the sacrificial material is removed as stated previously, and the vias are re-sealed in a vacuum coating process.04-30-2009
20100062597Interconnection for flip-chip using lead-free solders and having improved reaction barrier layers - An interconnection structure suitable for flip-chip attachment of microelectronic device chips to packages, comprising a two, three or four layer ball-limiting metallurgy including an adhesion/reaction barrier layer, and having a solder wettable layer reactive with components of a tin-containing lead free solder, so that the solderable layer can be totally consumed during soldering, but a barrier layer remains after being placed in contact with the lead free solder during soldering. One or more lead-free solder balls is selectively situated on the solder wetting layer, the lead-free solder balls comprising tin as a predominant component and one or more alloying components.03-11-2010
20110109405Low Temperature BI-CMOS Compatible Process For MEMS RF Resonators and Filters - A microelectromechanical system (MEMS) resonator or filter including a first conductive layer, one or more electrodes patterned in the first conductive layer which serve the function of signal input, signal output, or DC biasing, or some combination of these functions, an evacuated cavity, a resonating member comprised of a lower conductive layer and an upper structural layer, a first air gap between the resonating member and one or more of the electrodes, an upper membrane covering the cavity, and a second air gap between the resonating member and the upper membrane.05-12-2011

Patent applications by Leena Paivikki Buchwalter, Hopewell Junction, NY US

Stephen Leslie Buchwalter, Hopewell Junction, NY US

Patent application numberDescriptionPublished
20080251281ELECTRICAL INTERCONNECT STRUCTURE AND METHOD - An electrical structure and method of forming. The electrical structure includes a first substrate comprising a first electrically conductive pad, a second substrate comprising a second electrically conductive pad, and an interconnect structure electrically and mechanically connecting the first electrically conductive pad to the second electrically conductive pad. The interconnect structure comprises a non-solder metallic core structure, a first solder structure, and a second solder structure. The first solder structure electrically and mechanically connects a first portion of the non-solder metallic core structure to the first electrically conductive pad. The second solder structure electrically and mechanically connects a second portion of the non-solder metallic core structure to the second electrically conductive pad.10-16-2008
20090065555ELECTRICAL INTERCONNECT FORMING METHOD - An electrical structure method of forming. The method includes forming a plurality of individual metallic structures from metallic layer formed over a first substrate. A plurality of vias are formed within a second substrate. The plurality of vias are positioned over and surrounding the plurality of metallic structures. A portion of each via is filled with solder to form solder structure surrounding an exterior surface of each metallic structure. The first substrate is removed from the metallic structures. The metallic structures comprising the solder structures are positioned over a third substrate comprising a plurality of electrically conductive pads. The metallic structures comprising the solder structures are heated to a temperature sufficient to cause the solder to melt and form an electrical and mechanical connection between each metallic structure and an associated electrically conductive pad. The second substrate is removed from the individual metallic structures.03-12-2009
20100230143ELECTRICAL INTERCONNECT STRUCTURE - An electrical structure including a first substrate comprising a first electrically conductive pad, a second substrate comprising a second electrically conductive pad, and an interconnect structure electrically and mechanically connecting the first electrically conductive pad to the second electrically conductive pad. The interconnect structure comprises a non-solder metallic core structure, a first solder structure, and a second solder structure. The first solder structure electrically and mechanically connects a first portion of the non-solder metallic core structure to the first electrically conductive pad. The second solder structure electrically and mechanically connects a second portion of the non-solder metallic core structure to the second electrically conductive pad.09-16-2010
20100230474ELECTRICAL INTERCONNECT FORMING METHOD - An electrical interconnect forming method. The electrical interconnect includes a first substrate comprising a first electrically conductive pad, a second substrate comprising a second electrically conductive pad, and an interconnect structure electrically and mechanically connecting the first electrically conductive pad to the second electrically conductive pad. The interconnect structure comprises a non-solder metallic core structure, a first solder structure, and a second solder structure. The first solder structure electrically and mechanically connects a first portion of the non-solder metallic core structure to the first electrically conductive pad. The second solder structure electrically and mechanically connects a second portion of the non-solder metallic core structure to the second electrically conductive pad.09-16-2010
20100230475ELECTRICAL INTERCONNECT FORMING METHOD - An electrical interconnect forming method. The electrical interconnect includes a first substrate comprising a first electrically conductive pad, a second substrate comprising a second electrically conductive pad, and an interconnect structure electrically and mechanically connecting the first electrically conductive pad to the second electrically conductive pad. The interconnect structure comprises a non-solder metallic core structure, a first solder structure, and a second solder structure. The first solder structure electrically and mechanically connects a first portion of the non-solder metallic core structure to the first electrically conductive pad. The second solder structure electrically and mechanically connects a second portion of the non-solder metallic core structure to the second electrically conductive pad.09-16-2010

Patent applications by Stephen Leslie Buchwalter, Hopewell Junction, NY US