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Brzezinski, US
Daniel Brzezinski, Hudsonville, MI US
| Patent application number | Description | Published |
|---|---|---|
| 20100063670 | SYSTEM AND METHOD OF SYNCHRONIZING AN IN-VEHICLE CONTROL SYSTEM WITH A REMOTE SOURCE - The present application relates to an in-vehicle control system for synchronizing files with a remote source. The remote source includes a storage device configured to store a first file. The system includes a communications device capable of establishing a wireless communication link with the remote source. The communications device is configured to send, receive, or both send and receive files to and/or from the remote source. The system further includes a memory device configured to store a second file. The system yet further includes a data processing device coupled to the communications device, the data processing device configured to perform a comparison of the first file of the remote source and the second file of the memory device, wherein the data processing device is further configured to synchronize the file of the remote source and the file of the in-vehicle control system based on the comparison. | 03-11-2010 |
Dennis Brzezinski, Sunnyvale, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20100169739 | Poison bit error checking code scheme - In one embodiment, a method provides determining one of an occurrence and a non-occurrence of an event, the one of the occurrence and the non-occurrence resulting in an event determination; and processing a code having an event bit, said processing in accordance with the determination and the code, by determining if the event bit corresponds to the event determination, and if the event bit does not correspond to the event determination, encoding the code to generate a poison bit that corresponds to the event determination. | 07-01-2010 |
Dennis W. Brzezinski, Sunnyvale, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20090013211 | MEMORY CHANNEL WITH BIT LANE FAIL-OVER - Memory apparatus and methods utilizing multiple bit lanes may redirect one or more signals on the bit lanes. A memory agent may include a redrive circuit having a plurality of bit lanes, a memory device or interface, and a fail-over circuit coupled between the plurality of bit lanes and the memory device or interface. | 01-08-2009 |
| 20090319877 | SYSTEMS, METHODS, AND APPARATUSES TO TRANSFER DATA AND DATA MASK BITS IN A COMMON FRAME WITH A SHARED ERROR BIT CODE - Embodiments of the invention are generally directed to systems, methods, and apparatuses to transfer data and data mask bits in a common frame with a shared error bit code. A memory system uses data frames to transfer data between a host and a memory device. In some cases, the system may also transfer one or more data mask bits in a data frame (rather than via a separate bit lane). The system may generate an error bit checksum (such as a cyclic redundancy code or CRC) to cover the data bits and the data mask bits. In some embodiments, the data bits, data mask bits, and checksum bits are transferred in a common frame. | 12-24-2009 |
| 20100281315 | MEMORY CHANNEL WITH BIT LANE FAIL-OVER - Memory apparatus and methods utilizing multiple bit lanes may redirect one or more signals on the bit lanes. A memory agent may include a redrive circuit having a plurality of bit lanes, a memory device or interface, and a fail-over circuit coupled between the plurality of bit lanes and the memory device or interface. | 11-04-2010 |
| 20110066919 | MEMORY ERROR DETECTION AND/OR CORRECTION - An embodiment may include circuitry that may detect and/or correct at least one error in a data codeword that may include a data word, cyclical redundancy check (CRC) word, and parity word. The circuitry may select whether a portion of the CRC word indicates whether only a single processor has accessed the data word. The data word, CRC word, and the parity word may be accessible in respective distinct memory device sets that each may include one or more respective memory devices. If the circuitry detects, based at least in part upon the data codeword and CRC word, a CRC error, and the at least one error includes fewer than a first predetermined number of errors, the circuitry may determine in which of the one or more respective memory devices in the memory device sets the at least one error resides and may correct the at least one error. | 03-17-2011 |
| 20110131370 | DISABLING OUTBOUND DRIVERS FOR A LAST MEMORY BUFFER ON A MEMORY CHANNEL - Memory apparatus and methods utilizing multiple bit lanes may redirect one or more signals on the bit lanes. A memory agent may include a redrive circuit having a plurality of bit lanes, a memory device or interface, and a fail-over circuit coupled between the plurality of bit lanes and the memory device or interface. | 06-02-2011 |
| 20110138261 | METHOD AND SYSTEM FOR ERROR MANAGEMENT IN A MEMORY DEVICE - A method and system for error management in a memory device. In one embodiment of the invention, the memory device can handle commands and address parity errors and cyclic redundancy check errors. In one embodiment of the invention, the memory can detect whether a received command has any parity errors by determining whether the command bits or the address bits of the received command has any parity errors. If a parity error or cyclic redundancy check error in the received command is detected, an error handling mechanism is triggered to recover from the errant command. | 06-09-2011 |
| 20110145506 | Replacing Cache Lines In A Cache Memory - In one embodiment, the present invention includes a cache memory including cache lines that each have a tag field including a state portion to store a cache coherency state of data stored in the line and a weight portion to store a weight corresponding to a relative importance of the data. In various implementations, the weight can be based on the cache coherency state and a recency of usage of the data. Other embodiments are described and claimed. | 06-16-2011 |
| 20110154152 | ERROR CORRECTION MECHANISMS FOR 8-BIT MEMORY DEVICES - Described herein are 8-bit wide data error detection and correction mechanisms that require fewer memory chips and therefore provide reduces system complexity and reduced system power consumption as compared to traditional mechanisms. This technique relies on testing a fixed set of possible solutions in order to correct the fault. This error code provides a very high error detection rate, but requires a set of error trials to correct the detected faults. The extra correction latency for infrequent errors may be acceptable given a low frequency. For repeated corrections, a log may be maintained to simplify error correction. | 06-23-2011 |
Jacek Brzezinski, Lompoc, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20100096656 | CATIONIC CONJUGATED POLYELECTROLYTE ELECTRON INJECTION LAYERS ALTERED WITH COUNTER ANIONS HAVING OXIDATIVE PROPERTIES - Counter anions having oxidative properties alter the performance of solution processed multilayer polymer light emitting diodes (PLEDs) that use cationic conjugated polyelectrolytes (CPEs) as electron injection layers (EILs). In some versions, PLEDs with poly(2-methoxy-5-(2′-ethylhexyloxy)-1,4-phenylene vinylene) (MEH-PPV) emissive layers and cationic CPE EILs are altered with halide counter anions to exhibit a systematic increase in device performance. Exemplary oxidative counter anions are halide counter anions with F | 04-22-2010 |
Kurt L. Brzezinski, Mosinee, WI US
| Patent application number | Description | Published |
|---|---|---|
| 20110153515 | Distributed capture system for use with a legacy enterprise content management system - A distributed capture system is disclosed which enables digital content to be captured in various formats and interfaced with a plurality ECM) platforms which enables the distributed capture system to be seamlessly integrated with a customer's legacy ECM system. The system is configured to receive various financial records that are normally created at a financial institution, such as loan applications and customer signature cards, in various formats, such as Microsoft Word, PDF, and Printer Control Language (PCL). The financial records are directed to a virtual printer and converted to a TIFF format. The print stream associated with the text embedded in the TIFF image of the financial record is captured and compared with document classification template. The document classification template allows the document to be automatically classified and indexed. Documents are then sent to the ECM interface. The ECM interface allows financial records that are normally created at the financial institution to be converted to electronic form and stored in the financial institution's legacy ECM. By eliminating the need to purchase a new ECM, the need to convert existing data to the format of the legacy ECM is obviated. | 06-23-2011 |
Leonard Brzezinski, Redwood City, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20080313711 | MANAGING STATUS AND ACCESS FOR A VARIABLE SOURCE CONTENT STREAM - In one embodiment, a method can include: receiving rules in an interoperability server, the rules being related to access control for an endpoint coupled to a variable source content stream via a multicast network; and sending to the endpoint using in-band controls of the variable source content stream via the multicast network: a description of content streams available for selection by the endpoint; a procedure for selecting an available content stream; and permission for accessing the selected content stream, the permission being based on the rules. | 12-18-2008 |
Ronald John Brzezinski, Rexford, NY US
| Patent application number | Description | Published |
|---|---|---|
| 20110210233 | REINFORCEMENT SYSTEM FOR WIND TURBINE TOWER - A reinforcement system and a method for reinforcing a tower of a wind turbine are disclosed. The method includes providing a tower, the tower comprising at least one generally cylindrical tower section, the at least one tower section having an exterior wall and an interior wall defining a height and a thickness therebetween. The method further includes performing a structural analysis of the tower to identify potential load limiting locations and, after performing the structural analysis, mounting at least one reinforcing member to the interior wall of the at least one tower section to reinforce the at least one tower section at the potential load limiting locations. | 09-01-2011 |