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Bruno W. Garlepp
Bruno W. Garlepp, San Jose, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20090175326 | PARTIAL RESPONSE RECEIVER - A receive circuit for receiving a signal transmitted via an electric signal conductor. A first sampling circuit generates a first sample value that indicates whether the signal exceeds a first threshold level, and a second sampling circuit generates a second sample value that indicates whether the signal exceeds a second threshold level. A first select circuit receives the first and second sample values from the first and second sampling circuits and selects, according to a previously generated sample value, either the first sample value or the second sample value to be output as a selected sample value. | 07-09-2009 |
| 20090285272 | PARTIAL RESPONSE RECEIVER - An integrated circuit device having a receive circuit is disclosed. The receive circuit generates first and second sets of samples of incoming symbols during first and second time intervals, respectively. A select circuit selects, based at least in part on the first set of samples, at least one sample from the second set to be output as a received data value. The integrated circuit device further includes a transmit circuit to generate an output symbol during a third time interval. The output symbol has an amplitude based, at least in part, on a transmit data value for which an output symbol was generated during a time interval prior to the third time interval. | 11-19-2009 |
| 20100074314 | Margin Test Methods And Circuits - Described are methods and circuits for margin testing digital receivers. These methods and circuits prevent margins from collapsing in response to erroneously received data, and can thus be used in receivers that employ historical data to reduce intersymbol interference (ISI). Some embodiments detect receive errors for input data streams of unknown patterns, and can thus be used for in-system margin testing. Such systems can be adapted to dynamically alter system parameters during device operation to maintain adequate margins despite fluctuations in the system noise environment due to e.g. temperature and supply-voltage changes. Also described are methods of plotting and interpreting filtered and unfiltered error data generated by the disclosed methods and circuits. Some embodiments filter error data to facilitate pattern-specific margin testing. | 03-25-2010 |
| 20100142610 | PARTIAL RESPONSE RECEIVER - A signaling system is described. The signaling system comprises a transmit device, a receive device including a partial response receive circuit, and a signaling path coupling the transmit device and the receive device. The receive device observes an equalized signal from the signaling path, and includes circuitry to use feedback from the most recent previously resolved symbol to sample a currently incoming symbol. The transmit device equalizes transmit data to transmit the equalized signal, by applying weighting based on one or more data values not associated with the most recent previously resolved symbol value. | 06-10-2010 |
Bruno W. Garlepp, Austin, TX US
| Patent application number | Description | Published |
|---|---|---|
| 20100134153 | Low Latency Multi-Level Communication Interface - A multiphase receiver to compensate for intersymbol interference in the sampling of an input signal includes a first integrating receiver to integrate and sample data of the input signal on a first phase of a clock and a second integrating receiver to integrate and sample data of the input signal on a second phase of the clock. The multiphase receiver also includes an equalization circuit to adjust integration by the first integrating receiver dependent on a result of integration of data previously received by an integrating receiver distinct from the first integrating receiver, and to adjust integration by the second integrating receiver dependent on a result of integration of data previously received by an integrating receiver distinct from the second integrating receiver. | 06-03-2010 |
| 20110140741 | INTEGRATING RECEIVER WITH PRECHARGE CIRCUITRY - A multiphase receiver to compensate for intersymbol interference in the sampling of an input signal includes a first integrating receiver to integrate and sample data of the input signal on a first phase of a clock and a second integrating receiver to integrate and sample data of the input signal on a second phase of the clock. The multiphase receiver also includes an equalization circuit to adjust integration by the first integrating receiver dependent on a result of integration of data previously received by an integrating receiver distinct from the first integrating receiver, and to adjust integration by the second integrating receiver dependent on a result of integration of data previously received by an integrating receiver distinct from the second integrating receiver. | 06-16-2011 |
Bruno W. Garlepp, Sunnyvale, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20080297213 | Signaling with Superimposed Clock and Data Signals - A data receiver circuit includes an interface to receive an input signal that includes a data signal and a clock signal superimposed on the data signal. The data signal has an associated symbol rate and an associated symbol period equal to the reciprocal of the associated symbol rate. The clock signal has a frequency N times the associated symbol rate, where N is an integer. A phase-locked loop (PLL) coupled to the interface extracts the clock signal from the input signal to provide an extracted clock signal. A phase interpolator adjusts the phase of the extracted clock signal to provide a phase-adjusted extracted clock signal. A sampling circuit samples the data signal at a sampling point. The sampling circuit is synchronized to the phase-adjusted extracted clock signal. | 12-04-2008 |
| 20090327789 | Memory System with Calibrated Data Communication - A system includes a first integrated circuit device and a second integrated circuit device. The first device transmits a data sequence to the second integrated circuit device, and the second device samples the data sequence to produce receiver data. The second device then transmits the receiver data back to the first device. Within the first integrated circuit device, a comparison between the data sequence and the receiver data is performed, and based on the comparison, the first device generates information representative of a calibrated timing offset. The first device uses the information representative of the calibrated timing offset to adjust timing associated with transferring write data from the first integrated circuit to the second integrated circuit. | 12-31-2009 |
| 20100020861 | DFE Margin Test Methods and Circuits that Decouple Sample and Feedback Timing - Described are methods and circuits for margin testing digital receivers. These methods and circuits prevent margins from collapsing in response to erroneously received data, and can thus be used in receivers that employ historical data to reduce intersymbol interference (ISI). Some embodiments allows feedback timing to be adjusted independent of the sample timing to measure the effects of some forms of phase misalignment and jitter. | 01-28-2010 |