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Brueggen
Chris Brueggen, Allen, TX US
| Patent application number | Description | Published |
|---|---|---|
| 20110138132 | RESCINDING OWNERSHIP OF A CACHE LINE IN A COMPUTER SYSTEM - A method of rescinding ownership of a cache line in a computer system includes constructing a table of caching agent representations in which each caching agent representation is accompanied by a validity indicator. The method continues with receiving a cache line sharing list, with each entry of the cache line sharing list indicating the potential ownership of the cache line by one or more caching agent representations that correspond to an entry of the sharing list. The method also includes conveying a snoop packet to a caching agent when the logical conjunction of an entry of the cache line sharing list that corresponds to a caching agent representation and the accompanying validity indicator meets a predetermined Boolean condition. | 06-09-2011 |
Chris M. Brueggen, Allen, TX US
| Patent application number | Description | Published |
|---|---|---|
| 20110096786 | PAIRED NODE CONTROLLERS - In at least some embodiments, an apparatus comprises a pair of node controllers, each of the node controllers having a different processor assigned thereto. Each node controller is operable to selectively switch processor requests received from its assigned processor to the other node controller and to selectively switch responses to the processor requests to the other node controller. | 04-28-2011 |
Chris Michael Brueggen, Allen, TX US
| Patent application number | Description | Published |
|---|---|---|
| 20110032947 | RESOURCE ARBITRATION - A circuit includes queue buffers, a bid masking circuit, and a priority selection circuit. Each of the queue buffers carries packets of a respective message class selected from a set of message classes and asserts a respective bid signal indicating that the queue buffer carries a packet that is available for transmission. The bid masking circuit produces a masked vector of bid signals by selectively masking one or more of the bid signals asserted by the queue buffers based on credit available to transmit the packets and on cyclical masking of one or more of the bid signals asserted by ones of the queue buffers selected for packet transmission. The priority selection circuit selects respective ones of the queue buffers from which packets are transmitted based on the masked vector of bid signals produced by the bid masking circuit. | 02-10-2011 |
Chris Michael Brueggen, Richardson, TX US
| Patent application number | Description | Published |
|---|---|---|
| 20080263239 | Priority Selection Circuit - A circuit. The circuit includes a first selection module having first data input, second data input, first validation input, second validation input, selected data output, marker output, and presence output. A first validation signal received at the first validation input identifies whether or not a first data signal received at the first data input is valid; a second validation signal received at the second validation input identifies whether or not a second data signal received at the second data input is valid; a presence signal outputted at the presence output identifies whether or not at least one data signal is valid; and the first data input has an assigned selection priority higher than that assigned to the second data input. If at least one data signal is identified as valid, the valid data signal having the higher assigned priority is transferred to the selected data output. | 10-23-2008 |
| 20080270708 | System and Method for Achieving Cache Coherency Within Multiprocessor Computer System - A system and method are disclosed for achieving cache coherency in a multiprocessor computer system having a plurality of sockets with processing devices and memory controllers and a plurality of memory blocks. In at least some embodiments, the system includes a plurality of node controllers capable of being respectively coupled to the respective sockets of the multiprocessor computer, a plurality of caching devices respectively coupled to the respective node controllers, and a fabric coupling the respective node controllers, by which cache line request signals can be communicated between the respective node controllers. Cache coherency is achieved notwithstanding the cache line request signals communicated between the respective node controllers due at least in part to communications between the node controllers and the respective caching devices to which the node controllers are coupled. In at least some embodiments, the caching devices track remote cache line ownership for processor and/or input/output hub caches. | 10-30-2008 |
Kai-Uwe Brueggen, Mumbai IN
| Patent application number | Description | Published |
|---|---|---|
| 20090163554 | Use of CNI-OD Formulations for Controlling White Fly - Method of controlling eggs and nymphal stages of whitefly by the spray application of oil-based suspension concentrates containing at least one insecticide from the neonicotinyl series, at least one penetrant from the alcohol ethoxylate series, at least one vegetable oil, at least one nonionic surfactant and, if appropriate one or more additives. | 06-25-2009 |
| 20090298888 | Method of improving plant development and increasing the resistance of plants to soil-borne harmful fungi - The present invention relates to a method of improving plant growth and increasing the resistance of plants to soil-borne harmful fungi by directly admixing neonicotinoid-containing formulations into nutrient solutions conventionally employed in raising plants. | 12-03-2009 |
| 20090306147 | BIOLOGICAL EFFICACY OF AGROCHEMICAL COMPOSITIONS ON APPLICATION IN THE GROWTH SUBSTRATE SUITABLE FORMULATIONS AND USE THEREOF - In soil applications, the action of crop protection compositions comprising active compounds from the classes of the neonicotinoids, the pyrethroids, the butenolides, the ketoenols, the phenylpyrazoles or the fungicides can be improved by adjuvants. The present invention describes corresponding methods and suitable compositions. | 12-10-2009 |