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| 20090097017 | OPTICAL INSPECTION METHODS - Inspection methods. A method includes adhering an optical blocking layer directly onto and in direct mechanical contact with a semiconductor process wafer, the blocking layer being substantially opaque to a range of wavelengths of light; applying at least one layer over the blocking layer; and inspecting optically at least one wavelength at least one inspection area, the blocking layer extending substantially throughout the inspection area. An inspection method including adhering an optical absorbing layer to a semiconductor process wafer, where the absorbing layer is configured to substantially absorb a range of wavelengths of light; applying at least one layer over the absorbing layer; and inspecting optically at least one wavelength at least one inspection area of the process wafer. A manufacturing method including ascertaining if a defect is present within a photoresist layer, and changing a semiconductor manufacturing process to prevent the defect, if the defect is present. | 04-16-2009 |
| 20090150090 | SYSTEM AND METHOD FOR DETECTION AND PREVENTION OF INFLUX OF AIRBORNE CONTAMINANTS - An apparatus and method for detection of airborne contaminants and prevention of influx of the contaminants into an enclosed space, such as a vehicle cabin. A first sensor array samples exterior air prior to influx of the exterior air into the enclosed space. The first sensor array generates data uniquely corresponding to each contaminant. Data corresponding to predetermined contaminants is stored in computer memory. A user may also cause data corresponding to a contaminant selected by the user to be stored in the computer memory. Upon identification of a contaminant, an actuator is operative to control a position of a valve to prevent influx of the exterior air into the enclosed space. | 06-11-2009 |
| 20100112730 | OPTICAL INSPECTION METHODS - Inspection methods. A method includes adhering an optical blocking layer directly onto and in direct mechanical contact with a semiconductor process wafer, the blocking layer being substantially opaque to a range of wavelengths of light; applying at least one layer over the blocking layer; and inspecting optically at least one wavelength at least one inspection area, the blocking layer extending substantially throughout the inspection area. An inspection method including adhering an optical absorbing layer to a semiconductor process wafer, where the absorbing layer is configured to substantially absorb a range of wavelengths of light; applying at least one layer over the absorbing layer; and inspecting optically at least one wavelength at least one inspection area of the process wafer. A manufacturing method including ascertaining if a defect is present within a photoresist layer, and changing a semiconductor manufacturing process to prevent the defect, if the defect is present. | 05-06-2010 |
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| 20080213707 | Graded Spin-on Organic Antireflective Coating for Photolithography - An antireflective coating that contains at least two polymer components and comprises chromophore moieties and transparent moieties is provided. The antireflective coating is useful for providing a single-layer composite graded antireflective coating formed beneath a photoresist layer. | 09-04-2008 |
| 20080286683 | COMPOSITE STRUCTURES TO PREVENT PATTERN COLLAPSE - A method and a structure. The structure includes: a solid core comprising a first photoresist material, the core having a bottom surface on a substrate, a top surface and opposite first and second side surfaces between the top surface and the bottom surface; and a shell comprising a second photoresist material, the shell on the top surface of the substrate, the shell containing a cavity open to the top surface of the substrate, the shell formed over the top surface and the first and second side surfaces walls of the core, the core completely filling the cavity. The core is stiffer than the shell. The method includes: forming the core from a first photoresist layer and forming the shell from a second photoresist layer applied over the core. The core may be cross-linked to increase its stiffness. | 11-20-2008 |
| 20090075217 | TAPERED EDGE BEAD REMOVAL PROCESS FOR IMMERSION LITHOGRAPHY - A method and apparatus for forming a tapered photoresist edge. The method includes: forming a photoresist layer on a substrate; exposing a first annular region of the photoresist layer adjacent to a perimeter of the substrate to actinic radiation, the first annular region having a first outer perimeter proximate to a perimeter of the substrate and a first inner perimeter away from the perimeter of the substrate, the actinic radiation gradually decreasing in intensity from the first outer perimeter to the first inner perimeter; and developing the exposed first annular region of the photoresist layer to form a tapered profile in a second annular region of the photoresist layer, the second annular region having a second perimeter proximate to the perimeter of the substrate and a second inner perimeter away from the substrate perimeter, the profile gradually increasing in thickness from the second outer perimeter to the second inner perimeter. | 03-19-2009 |
| 20090262317 | TEST METHOD FOR DETERMINING RETICLE TRANSMISSION STABILITY - Methods, systems and apparatus for monitoring the state of a reticle by providing a reticle having a device exposure region in an imaging tool, defining one or more image fields across the device exposure region, and transmitting energy through the device exposure region. A detector detects the energy in the image field(s) at one or more testing intervals and a system control generates a transmission profile of average energy transmissions for each image field. Using this transmission profile, the state of the reticle is then determined at each testing interval followed by taking action based on the reticle state. The state of the reticle identifies whether the device exposure region has been deleteriously degraded, and as such, the reticle is no longer suitable for use. This is accomplished by determining if any average energy transmission of any image field across the reticle exceeds an allowable energy transmission threshold. | 10-22-2009 |
| 20100173247 | SUBSTRATE PLANARIZATION WITH IMPRINT MATERIALS AND PROCESSES - The present invention relates to planarization materials and methods of using the same for substrate planarization in photolithography. A planarization layer of a planarization composition is formed on a substrate. The planarization composition contains at least one aromatic monomer and at least one non-aromatic monomer. A substantially flat surface is brought into contact with the planarization layer. The planarization layer is cured by exposing to a first radiation or by baking The substantially flat surface is then removed. A photoresist layer is formed on the planarization layer. The photoresist layer is exposed to a second radiation followed by development to form a relief image in the photoresist layer. The relief image is then transferred into the substrate. | 07-08-2010 |
| 20110205509 | TEST METHOD FOR DETERMINING RETICLE TRANSMISSION STABILITY - Methods, systems and apparatus for monitoring the state of a reticle by providing a reticle having a device exposure region in an imaging tool, defining one or more image fields across the device exposure region, and transmitting energy through the device exposure region. A detector detects the energy in the image field(s) at one or more testing intervals and a system control generates a transmission profile of average energy transmissions for each image field. Using this transmission profile, the state of the reticle is then determined at each testing interval followed by taking action based on the reticle state. The state of the reticle identifies whether the device exposure region has been deleteriously degraded, and as such, the reticle is no longer suitable for use. This is accomplished by determining if any average energy transmission of any image field across the reticle exceeds an allowable energy transmission threshold. | 08-25-2011 |
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| 20080225284 | METHOD, APPARATUS, AND COMPUTER PROGRAM PRODUCT FOR OPTIMIZING INSPECTION RECIPES USING PROGRAMMED DEFECTS - A method and computer program product for implementing inspection recipe services are provided. The method includes defining a modified reticle pitch for use in inspecting programmed defects on a test structure, the modified reticle pitch extending the distance of one reticle field plus a portion of an adjacent reticle field on the test structure. The test structure includes a number of arrays linearly arranged on the test structure and spaced equidistant, and each of the arrays corresponds to a reticle field and includes a number of cells. The method also includes using the modified reticle field pitch and an alignment site on the test structure to perform a random mode inspection of the test structure. | 09-18-2008 |
| 20090051002 | ELECTRICAL FUSE HAVING A THIN FUSELINK - A thin semiconductor layer is formed and patterned on a semiconductor substrate to form a thin semiconductor fuselink on shallow trench isolation and between an anode semiconductor region and a cathode semiconductor region. During metallization, the semiconductor fuselink is converted to a thin metal semiconductor alloy fuselink as all of the semiconductor material in the semiconductor fuselink reacts with a metal to form a metal semiconductor alloy. The inventive electrical fuse comprises the thin metal semiconductor alloy fuselink, a metal semiconductor alloy anode, and a metal semiconductor alloy cathode. The thin metal semiconductor alloy fuselink has a smaller cross-sectional area compared with prior art electrical fuses. Current density within the fuselink and the divergence of current at the interface between the fuselink and the cathode or anode comparable to prior art electrical fuses are obtained with less programming current than prior art electrical fuses. | 02-26-2009 |
| 20090101956 | EMBEDDED TRENCH CAPACITOR HAVING A HIGH-K NODE DIELECTRIC AND A METALLIC INNER ELECTRODE - A deep trench is formed in a semiconductor substrate and a pad layer thereupon, and filled with a dummy node dielectric and a dummy trench fill. A shallow trench isolation structure is formed in the semiconductor substrate. A dummy gate structure is formed in a device region after removal of the pad layer. A first dielectric layer is formed over the dummy gate structure and a protruding portion of the dummy trench fill and then planarized. The dummy structures are removed. The deep trench and a cavity formed by removal of the dummy gate structure are filled with a high dielectric constant material layer and a metallic layer, which form a high-k node dielectric and a metallic inner electrode of a deep trench capacitor in the deep trench and a high-k gate dielectric and a metal gate in the device region. | 04-23-2009 |
| 20090184356 | DEEP TRENCH CAPACITOR IN A SOI SUBSTRATE HAVING A LATERALLY PROTRUDING BURIED STRAP - A deep trench is formed to a depth midway into a buried insulator layer of a semiconductor-on-insulator (SOI) substrate. A top semiconductor layer is laterally recessed by an isotropic etch that is selective to the buried insulator layer. The deep trench is then etched below a bottom surface of the buried insulator layer. Ion implantation is performed at an angle into the deep trench to dope the sidewalls of the deep trench beneath the buried insulator layer, while the laterally recessed sidewalls of the top semiconductor layer are not implanted with dopant ions. A node dielectric and trench fill materials are deposited into the deep trench. A buried strap has an upper buried strap sidewall that is offset from a lower buried strap sidewall and a deep trench sidewall. | 07-23-2009 |
| 20090242953 | SHALLOW TRENCH CAPACITOR COMPATIBLE WITH HIGH-K / METAL GATE - Forming a shallow trench capacitor in conjunction with an FET by forming a plurality of STI trenches; for the FET, implanting a first cell well having a first polarity between a first and a second of the STI trenches; for the capacitor, implanting a second cell well having a second polarity in an area of a third of the STI trenches; removing dielectric material from the third STI trench; forming a gate stack having a first portion located between the first and the second of the STI trenches and a second portion located over and extending into the third trench; and performing a source/drain implant of the same polarity as the second cell well, thereby forming a FET in the first cell well, and a capacitor in the second cell well. The second polarity may be opposite from the first polarity. An additional implant may reduce ESR in the second cell well. | 10-01-2009 |
| 20110092043 | DEEP TRENCH CAPACITOR IN A SOI SUBSTRATE HAVING A LATERALLY PROTRUDING BURIED STRAP - A deep trench is formed to a depth midway into a buried insulator layer of a semiconductor-on-insulator (SOI) substrate. A top semiconductor layer is laterally recessed by an isotropic etch that is selective to the buried insulator layer. The deep trench is then etched below a bottom surface of the buried insulator layer. Ion implantation is performed at an angle into the deep trench to dope the sidewalls of the deep trench beneath the buried insulator layer, while the laterally recessed sidewalls of the top semiconductor layer are not implanted with dopant ions. A node dielectric and trench fill materials are deposited into the deep trench. A buried strap has an upper buried strap sidewall that is offset from a lower buried strap sidewall and a deep trench sidewall. | 04-21-2011 |
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| 20080239683 | Method and Apparatus for Electrically Connecting Two Substrates Using a Land Grid Array Connector Provided with a Frame Structure Having Power Distribution Elements - A method and apparatus for electrically connecting two substrates using a land grid array (LGA) connector provided with a frame structure having power distribution elements. In an embodiment, the frame structure includes a frame having one or more conductive layers sandwiched between non-conductive layers. The frame may, for example, be a printed wire board (PWB) having power planes that distribute power from a first substrate (e.g., a system PWB) and/or a power cable to a second substrate (e.g., an electronic module). The frame includes one or more apertures configured to receive an LGA interposer for electrically connecting the two substrates. Preferably, the frame includes four apertures arranged in quadrants that each receive an interposer, and at least one power plane extends between two quadrants and/or adjacent to a peripheral edge of one or more quadrants in the form of stacked and/or parallel bus bars each defining a power domain. | 10-02-2008 |
| 20090111292 | Surface Mount Technology Pad Layout for Docking Connector Systems - A pad array for a surface mount technology board includes a front row ground pad as a single pad, followed by a signal pad. The ground pads internal to the array may be arranged as pairs of pads interconnected to each other, with sandwiching signal pads on the internal portion of the array. To minimize stress on connector wafers of large scale connectors, external rows of ground pads may be enlarged by a predetermined amount in a Y-direction to minimize potential formation of stress risers, while ensuring that electrical spacing requirements to adjacent signal leads may be preserved for optimal signal integrity. | 04-30-2009 |
| 20090193641 | Article Extraction / Insertion Tool and Assembly - A tool assembly for removing an article from, or inserting an article onto, a printed circuit board which includes a tool housing having a handle portion and an article receiving portion, a plate slidable within the housing, the plate having a handle portion at a first end adjacent to the handle portion of the housing and two receiving portions at a second end, and two lever arms within the housing, each lever arm having a first end pinned to the housing and a second end of each lever arm inserted into the receiving portion of the plate such that each of the lever arms pivots about the pinned first end upon movement of the plate. The tool further comprises a pair of flexible rods located in respective recessed channels on either side of the article receiving portion, with one end of the flexible rods affixed to a first end of each of the lever arms, each of the flexible rods having a free end for interacting with an article retention device. The tool assembly may also include a tool guide for aligning the tool with a desired portion of a printed circuit board. | 08-06-2009 |
| 20090321125 | Plastic Land Grid Array (PLGA) Module and Printed Wiring Board (PWB) With Enhanced Contact Metallurgy Construction - An enhanced contact metallurgy construction for plastic land grid array (PLGA) modules and printed wiring boards (PWBs). The PWB may, for example, have subcomposite laminate construction and/or a double-sided LGA site. A plurality of preform contacts are each respectively soldered to one of a plurality of metal pads on a PLGA module carrier and/or a PWB. Each of the preform contacts comprises a metal preform base (e.g., copper, nickel) soldered to one of the plurality of metal pads and an electrolytic noble metal plating (e.g., gold) over the metal preform base. An electrolytic non-noble metal underplating (e.g., nickel) may be interposed between the metal preform base and the electrolytic noble metal plating. In one embodiment, the electrolytic non-noble metal underplating is 80-400 microinches thick to provide an enhanced diffusion barrier, and the electrolytic noble metal plating is 30-60 microinches thick and incorporates one or more hardening agents to provide enhanced wear and corrosion resistance. | 12-31-2009 |
| 20100184305 | COMPENSATION OF THERMAL EXPANSION IN SMT INTERCONNECTS - The present invention relates to a method of providing end and center locating connectors in interconnects between surface mount technology (SMT) connectors and printed circuit boards (PCBs). The connectors are adapted to maintain their connection even when the printed circuit board and/or the SMT connector expands or contracts. | 07-22-2010 |
