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Brisbin
Brian George Brisbin, Toronto CA
| Patent application number | Description | Published |
|---|---|---|
| 20120019016 | Holding Article For Hand-Holdable Electronic Devices - A joint hand and hand-holdable electronic device holdable article for being releasably retained on the device, the article having (i) device-retaining means for releasably retaining the article to the device; and (ii) hand-receiving means for releasably receiving a user's hand in abutment whereby the article receives the hand in a non-grip balanced stress-free manner. Use of the article with preferably a tablet computer or display hand-holdable device prevents or reduces ache, stress and other discomfort to the hand. | 01-26-2012 |
Douglas Brisbin, San Jose, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20090146192 | MOS transistor and method of forming the MOS transistor with a SiON etch stop layer that protects the transistor from PID and hot carrier degradation - A MOS transistor is formed with a dual-layer silicon oxynitride (SiON) etch stop film that protects the transistor from plasma induced damage (PID) and hot carrier degradation, thereby improving the reliability of the transistors. The first SiON layer is formed with SiH | 06-11-2009 |
| 20090254872 | Method for Designing and Manufacturing a PMOS Device with Drain Junction Breakdown Point Located for Reduced Drain Breakdown Voltage Walk-in - A PMOS device can be designed and manufactured in accordance with the invention to locate its drain junction breakdown point and maximum impact ionization point to reduce or eliminate drain breakdown voltage walk-in. In some embodiments, the drain junction breakdown point and maximum impact ionization point are located sufficiently far from the gate that the device exhibits no significant drain breakdown voltage walk-in. The device can be a high voltage power transistor having an extended drain region including a P-type lightly doped drain (P-LDD) implant, with drain junction breakdown and maximum impact ionization points appropriately located by controlling the implant dose employed to produce the P-LDD implant. Other aspects of the invention are methods for designing a PMOS device including by determining relative locations of the gate and at least one of the drain junction breakdown and maximum impact ionization points to reduce drain breakdown voltage walk-in, and methods for manufacturing integrated circuits including any embodiment of the PMOS device of the invention. | 10-08-2009 |
Lindsay M. Brisbin, Redondo Beach, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20090284436 | PHASED ARRAY ANTENNA RADIATOR ASSEMBLY AND METHOD OF FORMING SAME - A phased array antenna radiator assembly that in one embodiment has a thermally conductive foam substrate, a plurality of metal radiating elements bonded to the foam substrate, and a radome supported adjacent the metal radiating elements. In another embodiment a phased array antenna radiator assembly is disclosed that has a thermally conductive substrate, a plurality of metal radiating elements bonded to the thermally conductive substrate, a radome supported adjacent the metal radiating elements, and an electrostatically dissipative adhesive in contact with the radiating elements for bonding the radome to the thermally conductive substrate. | 11-19-2009 |