| Patent application number | Description | Published |
| 20080274147 | Dry Limited Use Cloth - The present invention is directed to a dry cleansing cloth that comprises at least one personal care composition imparted to the cloth, wherein the composition acts as a visual indicator of the compositions depletion with each use, eventually signaling the consumer for the need of a replacement cloth. Accordingly, the cloth of the present invention may be any suitable limited use substrate, including wovens, nonwovens, films, and combinations thereof. Preferably, the limited use cloth comprises a nonwoven substrate, wherein the nonwoven substrates may include, but are not limited to airlaid fabrics, wetlaid fabrics, spunlace fabrics, spunbond fabrics, meltblown fabrics, coform fabrics, entangled spunbond fabrics, and combinations thereof. | 11-06-2008 |
| Patent application number | Description | Published |
| 20080281996 | Latency Insensitive FIFO Signaling Protocol - Data from a source domain operating at a first data rate is transferred to a FIFO in another domain operating at a different data rate. The FIFO buffers data before transfer to a sink for further processing or storage. A source side counter tracks space available in the FIFO. In disclosed examples, the initial counter value corresponds to FIFO depth. The counter decrements in response to a data ready signal from the source domain, without delay. The counter increments in response to signaling from the sink domain of a read of data off the FIFO. Hence, incrementing is subject to the signaling latency between domains. The source may send one more beat of data when the counter indicates the FIFO is full. The last beat of data is continuously sent from the source until it is indicated that a FIFO position became available; effectively providing one more FIFO position. | 11-13-2008 |
| 20090031155 | Method and Apparatus for Adaptive Voltage Scaling Based on Instruction Usage - Different software applications may use a set of instructions having critical timing paths less than a worst case critical timing path of a processor complex. For such applications, a supply voltage may be reduced while still maintaining the clock frequency necessary to meet the application's performance requirements. In order to reduce the supply voltage, an adaptive voltage scaling method is used. A critical path is selected from a plurality of critical paths for analysis on emulation logic to determine an attribute of the selected critical path during on chip functional operations. The selected critical path is representative of the worst case critical path to be in operation during a program execution. During on-chip functional operations, a voltage is controlled in response to the attribute, wherein the voltage supplies power to a power domain associated with the plurality of critical paths. The reduction in voltage reduces power drain based on instruction set usage allowing battery life to be extended. | 01-29-2009 |
| 20090210663 | Power Efficient Instruction Prefetch Mechanism - A processor includes a conditional branch instruction prediction mechanism that generates weighted branch prediction values. For weakly weighted predictions, which tend to be less accurate than strongly weighted predictions, the power associating with speculatively filling and subsequently flushing the cache is saved by halting instruction prefetching. Instruction fetching continues when the branch condition is evaluated in the pipeline and the actual next address is known. Alternatively, prefetching may continue out of a cache. To avoid displacing good cache data with instructions prefetched based on a mispredicted branch, prefetching may be halted in response to a weakly weighted prediction in the event of a cache miss. | 08-20-2009 |
| 20090313695 | Methods and Systems for Checking Run-Time Integrity of Secure Code Cross-Reference to Related Applications - Methods and systems to guard against attacks designed to replace authenticated, secure code with non-authentic, unsecure code and using existing hardware resources in the CPU's memory management unit (MMU) are disclosed. In certain embodiments, permission entries indicating that pages in memory have been previously authenticated as secure are maintained in a translation lookaside buffer (TLB) and checked upon encountering an instruction residing at an external page. A TLB permission entry indicating permission is invalid causes on-demand authentication of the accessed page. Upon authentication, the permission entry in the TLB is updated to reflect that the page has been authenticated. As another example, in certain embodiments, a page of recently authenticated pages is maintained and checked upon encountering an instruction residing at an external page. | 12-17-2009 |
| 20110140752 | Adaptive Clock Generators, Systems, and Methods - Adaptive clock generators, systems, and related methods than can be used to generate a clock signal for a functional circuit to avoid or reduce performance margin are disclosed. In certain embodiments, a clock generator autonomously and adaptively generates a clock signal according to a delay path(s) provided in a delay circuit(s) relating to a selected delay path(s) in the functional circuit(s). The clock generator includes a delay circuit(s) adapted to receive an input signal and delay the input signal by an amount relating to a delay path(s) of a functional circuit(s) to produce an output signal. A feedback circuit is coupled to the delay circuit(s) and responsive to the output signal, wherein the feedback circuit is adapted to generate the input signal back to the delay circuit(s) in an oscillation loop configuration. The input signal can be used to provide a clock signal to the functional circuit(s). | 06-16-2011 |
| 20110241423 | Circuits, Systems and Methods to Detect and Accommodate Power Supply Voltage Droop - Circuits, systems, and methods for monitoring a power supply voltage and determining if the power supply voltage has drooped are disclosed. In one embodiment, a voltage monitoring circuit is provided and configured to determine if the power supply voltage supplied to a functional circuit has drooped. When no droop of the power supply voltage is detected, the voltage monitoring circuit is configured to provide an indication to the functional circuit to operate in a first mode. When droop of the power supply voltage is detected, the voltage monitoring circuit is configured to provide an indication to the functional circuit to operate in a second mode. In this manner, operating margin in the power supply may be reduced since the functional circuit may be configured to properly operate when a voltage droop of the power supply voltage occurs. | 10-06-2011 |
| Patent application number | Description | Published |
| 20090088023 | Locking Receptacle For Engaging A USB Device - A locking receptacle for engaging a USB device is provided. The locking receptacle comprising a four sided header with a top opening at the top of the header and a bottom opening at the bottom of the header, the top opening and the bottom opening for USB connections; the header connected to a pivotable locking tip on one side, the pivotable locking tip located to engage a standard opening on a side of a USB plug of a USB device when the USB plug is fully inserted in the locking receptacle; and the pivotable locking tip connected to a lever for pivoting the locking tip. | 04-02-2009 |
| 20100079936 | TOOL-LESS BACKPLANE RETENTION FOR COMPUTER HARDWARE - An apparatus is provided and includes a housing, including a housing mating device, through which an installation path for an assembly is defined with a space in which a first part is positioned, a backplane body having opposing faces on which a second part and a backplane mating device are respectively disposed, and a hub, in which a hub mating device is defined, and from which a two-stage mating device extends, the two-stage mating device including first and second elastically coupled stages. The hub and the backplane body are coupled to form the assembly and the assembly is installed/removed in/from the space with the second stage of the two-stage mating device elastically hooked by the housing mating device or released from the housing mating device and the first and second stages of the two-stage mating device biasing the hub and the backplane body to remain coupled. | 04-01-2010 |
| 20120255153 | TOOL-LESS BACKPLANE RETENTION FOR COMPUTER HARDWARE - An apparatus is provided and includes a housing, including a housing mating device, through which an installation path for an assembly is defined with a space in which a first part is positioned, a backplane body having opposing faces on which a second part and a backplane mating device are respectively disposed, and a hub, in which a hub mating device is defined, and from which a two-stage mating device extends, the two-stage mating device including first and second elastically coupled stages. The hub and the backplane body are coupled to form the assembly and the assembly is installed/removed in/from the space with the second stage of the two-stage mating device elastically hooked by the housing mating device or released from the housing mating device and the first and second stages of the two-stage mating device biasing the hub and the backplane body to remain coupled. | 10-11-2012 |