| Patent application number | Description | Published |
|---|
| 20080244185 | Reduction of cache flush time using a dirty line limiter - The invention relates to a method for reducing cache flush time of a cache in a computer system. The method includes populating at least one of a plurality of directory entries of a dirty line directory based on modification of the cache to form at least one populated directory entry, and de-populating a pre-determined number of the plurality of directory entries according to a dirty line limiter protocol causing a write-back from the cache to a main memory, where the dirty line limiter protocol is based on a number of the at least one populated directory entry exceeding a pre-defined limit. | 10-02-2008 |
| 20080288556 | MAINTAINING MEMORY CHECKPOINTS ACROSS A CLUSTER OF COMPUTING NODES - A method and system for increasing reliability and availability of a multi-processor network. A system includes a network with at least two nodes, with each node comprising a multi-processor unit (mpu) and memory. The mpu includes one or more processors and a wiretap unit. The wiretap unit and the memory included in the node are coupled to the processors in the node. The wiretap unit is configured to monitor memory accesses of the processors and convey data indicative of such accesses to a second node. The second node maintains a replica of memory in the first node, and is configured to undo modifications to the memory if needed. In the event of a hardware or software fault, the nodes are configured to restart the application on another node. | 11-20-2008 |
| 20090067851 | MULTI-CHIP SYSTEMS WITH OPTICAL BYPASS - Embodiments of a system that includes an array of single-chip modules (CMs) are described. This array includes a first CM, a second CM coupled to the first CM, and a third CM coupled to the second CM. A given CM, which can be the first CM, the second CM or the third CM, includes a semiconductor die that is configured to communicate data signals with other CMs through electromagnetically coupled proximity communication. These proximity connectors are proximate to a surface of the semiconductor die. Moreover, the first CM and the third CM are configured to optically communicate optical signals with each other via the second CM through an optical signal path. | 03-12-2009 |
| 20090086746 | DIRECT MESSAGING IN DISTRIBUTED MEMORY SYSTEMS - A system and method for sending a cache line of data in a single message is described. An instruction issued by a processor in a multiprocessor system includes an address of a message payload and an address of a destination. Each address is translated to a physical address and sent to a scalability interface associated with the processor and in communication with a system interconnect. Upon translation the payload of the instruction is written to the scalability interface and thereafter communicated to the destination. According to one embodiment, the translation of the payload address is accomplished by the processor while in another embodiment the translation occurs at the scalability interface. | 04-02-2009 |
| 20090089511 | HYBRID CACHE COHERENCE USING FINE-GRAINED HARDWARE MESSAGE PASSING - Multiprocessor systems conducting operations utilizing global shared memory must ensure that the memory is coherent. A hybrid system that combines hardware memory transactions with that of direct messaging provides memory coherence with minimal overhead requirement or bandwidth demands. Memory access transactions are intercepted and converted to direct messages which are then communicated to a target and/or remote node. Thereafter the message invokes a software handler which implements the cache coherence protocol. The handler uses additional messages to invalidate or fetch data in other caches, as well as to return data to the requesting processor. These additional messages are converted to appropriate hardware transactions by the destination system interface hardware. | 04-02-2009 |
| 20100014427 | ARBITRATION SCHEME FOR AN OPTICAL BUS - A method of arbitrating data transmissions to prevent data collisions in an optical data interconnect system including a transmitting node, a plurality of receiving nodes, and one or more remaining nodes connected through an optical data channel. The method involves transmitting a transmission request signal from the transmitting node over an arbitration channel corresponding to the transmitting node, monitoring, at the transmitting node, a plurality of arbitration channels corresponding to each of the plurality of receiving nodes and the one or more remaining nodes at the transmitting node for a predetermined period of time, determining a start time for a data transmission from the transmitting node based on the monitored signals to prevent a data collision, and initiating a data transmission of a data signal from the transmitting node over the optical data channel at the determined start time. | 01-21-2010 |
| 20100014852 | CSMA/CD OPTICAL INTERCONNECT SCHEME - A method of detecting transmission collisions in an optical data interconnect system including a transmitting node, a plurality of receiving nodes, and one or more remaining nodes connected through an optical data channel. The method includes initiating a data transmission of a data signal from the transmitting node over the optical data channel, transmitting a first collision detect signal from the transmitting node throughout a duration of the data transmission where the first collision detect signal is transmitted over an optical detection channel corresponding to the transmitting node, monitoring at the transmitting node of the optical data interconnect system for a predetermined period of time, where the optical data interconnect system further includes a plurality of optical collision detection channels corresponding to each of the plurality of receiving nodes and the one or more remaining nodes, and identifying a transmission collision when a second collision signal is received through one of the plurality of optical collision detection channels at the transmitting node during the predetermined period of time. | 01-21-2010 |
| 20100017572 | TRANSACTIONAL MEMORY SUPPORT FOR NON-COHERENT SHARED MEMORY SYSTEMS USING SELECTIVE WRITE THROUGH CACHES - A method of controlling memory operations in a transactional shared memory system having a plurality of nodes connected through an interconnect network. The method includes initiating a memory operation at a first node including a first memory controller and a transaction table where the transaction table is configured to store a list of nodes affected by the memory operation, transmitting a store request signal through the interconnect network to a second node including a second memory controller and an access table where the store request signal includes memory operation data from the first memory controller, storing memory operation data to the access table in entries corresponding to one or more memory addresses affected by the memory operation, identifying a memory conflict with one or more nodes in the list of nodes when the one or more memory addresses affected by the memory operation are also affected by one or more conflicting transactions listed in the access table, transmitting an abort signal from the second node to each of the one or more nodes corresponding to the memory conflict, and transmitting an intent to commit signal from the first node to the second node. | 01-21-2010 |
| 20100266240 | MULTI-CHIP SYSTEM INCLUDING CAPACITIVELY COUPLED AND OPTICAL COMMUNICATION - Embodiments of a system are described. This system includes an array of chip modules (CMs) and a baseplate, where the baseplate is configured to communicate data signals via optical communication. Moreover, the array includes first CMs mechanically coupled to first alignment features on the baseplate, and adjacent second CMs mechanically coupled to second alignment features on the baseplate. In this array, a given first CM is electrically coupled to a given set of electrical proximity connectors. Additionally, the array includes bridge components, wherein a given bridge component is electrically coupled to the second SCM and another set of electrical proximity connectors, which is electrically coupled to the set of electrical proximity connectors, thereby facilitating communication of other data signals between adjacent first CMs and second CMs via electrical proximity communication. Moreover, the given bridge component is optically coupled to the baseplate, thereby facilitating optical communication of the data signals between CMs via the baseplate. | 10-21-2010 |
| 20100266276 | BROADBAND AND WAVELENGTH-SELECTIVE BIDIRECTIONAL 3-WAY OPTICAL SPLITTER - Embodiments of a bidirectional 3-way optical splitter are described. This bidirectional 3-way optical splitter includes an optical splitter having: a first external node, a second external node, a third external node, and a fourth external node. In one mode of operation, the optical splitter may be configured to receive an external input optical signal on the first external node and to provide external output optical signals on the other external nodes. Moreover, in another mode of operation, the optical splitter may be configured to receive the external input optical signal on the third external node and to provide the external output optical signals on the other external nodes. | 10-21-2010 |
