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Brian Smith
Brian Smith, Westfield, MA US
| Patent application number | Description | Published |
|---|---|---|
| 20110020750 | LITHOGRAPHIC IMAGING AND PRINTING WITH WET, POSITIVE-WORKING PRINTING MEMBERS - Embodiments of the present invention involve printing members that avoid ablation imaging mechanisms and, as a result, crosslinked topmost layers. Topmost layers as described herein exhibit good thermal stability and durability during printing, but can be cleaned (and thereby removed from unimaged areas) with water or aqueous cleaning fluids following imaging. It is found, in some embodiments, that the viability of certain topmost layers can be critically dependent on the nature of the underlying substrate, e.g., in terms of texture and/or surface volume. | 01-27-2011 |
Brian Smith, Rolla, MO US
| Patent application number | Description | Published |
|---|---|---|
| 20100170868 | SPIN-ON SPACER MATERIALS FOR DOUBLE- AND TRIPLE-PATTERNING LITHOGRAPHY - Novel double- and triple-patterning methods are provided. The methods involve applying a shrinkable composition to a patterned template structure (e.g., a structure having lines) and heating the composition. The shrinkable composition is selected to possess properties that will cause it to shrink during heating, thus forming a conformal layer over the patterned template structure. The layer is then etched to leave behind pre-spacer structures, which comprise the features from the pattern with remnants of the shrinkable composition adjacent the feature sidewalls. The features are removed, leaving behind a doubled pattern. In an alternative embodiment, an extra etch step can be carried out prior to formation of the features on the template structure, thus allowing the pattern to be tripled rather than doubled. | 07-08-2010 |
Brian Smith, Mountain View, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20090153211 | Integrated circuit device core power down independent of peripheral device operation - In an integrated circuit device, a circuit for maintaining asserted values on an input output pin of the device when a functional block of the device is placed in a sleep mode. The circuit includes an interface for coupling a functional block of a processor to an input and output pin and an output storage element coupled to the interface for storing a current value of the input output pin. The circuit further includes a sleep mode enable for controlling the output storage element to store the current value of the input output pin prior to the functional block being entering a sleep mode and cause the current value of the input output pin to remain asserted after the functional block is in sleep mode. The sleep mode enable is also to deactivate the storage element when the sleep mode is exited. | 06-18-2009 |
| 20090201082 | INTEGRATED CIRCUIT DEVICE HAVING POWER DOMAINS AND PARTITIONS BASED ON USE CASE POWER OPTIMIZATION - A programmable SoC (system on a chip) having optimized power domains and power islands. The SoC is an integrated circuit device including a plurality of power domains, each of the power domains having a respective voltage rail to supply power to the power domain. A plurality of power islands are included within the integrated circuit device, wherein each power domain includes at least one power island. A plurality of functional blocks are included within the integrated circuit device, wherein each power island includes at least one functional block. Each functional block is configured to provide a specific device functionality. The integrated circuit device adjusts power consumption in relation to a requested device functionality by individually turning on or turning off power to a selected one or more power domains, and for each turned on power domain, individually power gating one or more power islands. | 08-13-2009 |
| 20090204834 | SYSTEM AND METHOD FOR USING INPUTS AS WAKE SIGNALS - A system and method for waking up a portion of a programmable system on a chip (SoC). The system includes a power management unit for controlling power levels to the SoC and one or more inputs for receiving inputs from a coupled device. The system further includes a power management interface coupled to the one or more inputs. The power management interface signals the power management unit to adjust power levels to the SoC in response to receiving a signal via the one or more inputs corresponding to a wake event. | 08-13-2009 |
| 20090204835 | USE METHODS FOR POWER OPTIMIZATION USING AN INTEGRATED CIRCUIT HAVING POWER DOMAINS AND PARTITIONS - In a programmable SoC (system-on-a-chip) integrated circuit device, a method for optimizing power efficiency for a requested device functionality. The method includes determining a requested device functionality, and in response to the requested device functionality, turning on power for a selected one or more power domains out of a plurality of power domains included within the integrated circuit device. Each of the power domains has its own respective voltage rail to obtain power. The method further includes turning on one or more power islands out of a plurality of power islands included within the integrated circuit device. The requested device functionality is then implemented using one or more functional blocks wherein each functional block is configured to provide a specific device functionality. | 08-13-2009 |
| 20090256607 | POWERED RING TO MAINTAIN IO INDEPENDENT OF THE CORE OF AN INTEGRATED CIRCUIT DEVICE - In an integrated circuit device, a power circuit for maintaining asserted values on an input output pin of the device when a functional block of the device is placed in a sleep mode. The device includes a power circuit disposed along the periphery of the device, the power circuit configured to maintain power when the device is placed in a low-power mode. A plurality of input output blocks are included in the device and are for receiving external inputs for the integrated circuit device and for providing outputs from the integrated circuit device. The power circuit is coupled to provide power to at least one of the input output blocks to maintain state when the integrated circuit device is in the low-power mode. | 10-15-2009 |
| 20090259425 | SYSTEM AND METHOD FOR INTEGRATED CIRCUIT CALIBRATION - A system and method for calibrating an integrated circuit. The method includes configuring a first impedance for a first output of the integrated circuit according to a first configuration code and measuring a first voltage at the first output which corresponds to the first configuration code. The method further includes configuring a second impedance for a second output of the integrated circuit according to a second configuration code and measuring a second voltage at the second output which corresponds to the second configuration code. A determination of which of the first voltage and the second voltage is nearest to a predetermined voltage value. Based on the voltage determination, the integrated circuit is configured according a code of said first and second codes that corresponds to the voltage nearest to the predetermined voltage. | 10-15-2009 |
| 20090309243 | MULTI-CORE INTEGRATED CIRCUITS HAVING ASYMMETRIC PERFORMANCE BETWEEN CORES - An integrated circuit in one embodiment includes asymmetric cores and an asymmetric core control circuit. At least one of the asymmetric cores is a different implementation of substantially the same function or subset of functionality as another core. The asymmetric core control circuit determines a performance parameter of an integrated circuit. The performance parameter may be the workload, the operating frequency, power consumption, quality of service, operating temperature or the like of the integrated circuit or a given portion of the integrated circuit. If the performance parameter is within a first range, the asymmetric core control circuit utilizes a first core to perform a function of the integrated circuit and idles a second core that is a different implementation of substantially the same function. If the performance parameter is within a second range, the core control circuit utilizes the second core to perform the function and idles the first core. | 12-17-2009 |
| 20110213947 | System and Method for Power Optimization - A technique for reducing the power consumption required to execute processing operations. A processing complex, such as a CPU or a GPU, includes a first set of cores comprising one or more fast cores and second set of cores comprising one or more slow cores. A processing mode of the processing complex can switch between a first mode of operation and a second mode of operation based on one or more of the workload characteristics, performance characteristics of the first and second sets of cores, power characteristics of the first and second sets of cores, and operating conditions of the processing complex. A controller causes the processing operations to be executed by either the first set of cores or the second set of cores to achieve the lowest total power consumption. | 09-01-2011 |
| 20110213950 | System and Method for Power Optimization - A technique for reducing the power consumption required to execute processing operations. A processing complex, such as a CPU or a GPU, includes a first set of cores comprising one or more fast cores and second set of cores comprising one or more slow cores. A processing mode of the processing complex can switch between a first mode of operation and a second mode of operation based on one or more of the workload characteristics, performance characteristics of the first and second sets of cores, power characteristics of the first and second sets of cores, and operating conditions of the processing complex. A controller causes the processing operations to be executed by either the first set of cores or the second set of cores to achieve the lowest total power consumption. | 09-01-2011 |
| 20110213998 | System and Method for Power Optimization - A technique for reducing the power consumption required to execute processing operations. A processing complex, such as a CPU or a GPU, includes a first set of cores comprising one or more fast cores and second set of cores comprising one or more slow cores. A processing mode of the processing complex can switch between a first mode of operation and a second mode of operation based on one or more of the workload characteristics, performance characteristics of the first and second sets of cores, power characteristics of the first and second sets of cores, and operating conditions of the processing complex. A controller causes the processing operations to be executed by either the first set of cores or the second set of cores to achieve the lowest total power consumption. | 09-01-2011 |
Brian Smith, Encinitas, CA US
Brian Smith, Kettering, OH US
| Patent application number | Description | Published |
|---|---|---|
| 20090188396 | OVEN WITH WIRELESS TEMPERATURE SENSOR FOR USE IN MONITORING FOOD TEMPERATURE - An oven includes a housing including a heating chamber. A door has an open position for allowing operator access to the heating chamber and a closed position for preventing user access to the heating chamber. A heating system heats a food product located within the heating chamber. A wireless temperature sensor is configured to be inserted into the food product by an operator for measuring food product temperature and to provide a wireless signal indicative of food product temperature. An oven control system includes a sensor communicator for receiving the temperature indicative signal from the wireless temperature sensor. The oven control system operates in response to the wireless signal. | 07-30-2009 |
Brian Smith, Dallas, TX US
| Patent application number | Description | Published |
|---|---|---|
| 20090168980 | REPORT DATA CAPTURE VIA BILLING MODULE - A system for reporting telecommunications system usage data related to a telecommunications service. The system includes a network controller that captures telecommunications service billing data and reporting data, and populates a base module with the billing data and a local use module with the reporting data. The system also includes a storage system that stores the base module and the appended local use module, and a reporting system that generates billing reports from the base module and various user-selectable reports from the appended local use module. | 07-02-2009 |
Brian Smith, Ontario CA
| Patent application number | Description | Published |
|---|---|---|
| 20090157353 | Ethernet service testing and verification - A method of testing a service connection within a container in an Ethernet network comprises coupling a test device to a port on a node in a path that includes the container, switching traffic of the service connection to the port, measuring selected parameters of the switched traffic in the test device, and using the measured parameters to evaluate the performance of the service connection. In one implementation, the switching uses service and container identifications, and switching the traffic to the test device is based on the service and container identifications. The test device may be capable of inserting traffic within the service connection, and the container may be a tunnel. | 06-18-2009 |
Brian Smith, Melbourne, FL US
| Patent application number | Description | Published |
|---|---|---|
| 20090143927 | System and method for dispatching by exception - A system and method for controlling the movement of plural trains over a rail network, where the rail network is divided into at least one control area with a dispatcher assigned to manage the movement of trains in a control area by predicting the occurrence of events along the network based on the movement plan and prompting the dispatcher to provide information or take specified actions relating to the predicted events. | 06-04-2009 |
Brian Smith, Ft. Lauderdale, FL US
| Patent application number | Description | Published |
|---|---|---|
| 20090111564 | Bonus actuator attachment for gaming machines - The present invention relates to a bonus actuator attachment for a slot or gaming machine. More specifically, the present invention relates to an apparatus and method of selectively triggering a first bonus triggering event, by way of a bonus actuator attachment, so as to make the player eligible to participate in a bonus game upon the happening of a second bonus triggering event. Actuation of the bonus actuator attachment is a first triggering event wherein the gaming machine recognizes that the player wishes to be eligible for a bonus round within the gaming machine. The first triggering event may also require that the player make an additional wager separate from any initial wager on the game wherein the additional wager is solely to make the player eligible for a second bonus triggering event and, ultimately, a bonus round of the gaming machine. | 04-30-2009 |
Brian Smith, Rochester, MN US
| Patent application number | Description | Published |
|---|---|---|
| 20080307194 | Parallel, Low-Latency Method for High-Performance Deterministic Element Extraction From Distributed Arrays - The present invention provides a system and method for extracting elements from distributed arrays on a parallel processing system. The system includes a module that populates a local array with elements from input, a module that submits a largest element value in the local array and a processor ID for a local processor, and a module that determines a globally largest element value from the largest element values submitted by each one of the plurality of processors. The system further includes a module that broadcasts a winning globally largest element value and winning processor ID to the plurality of processors, and a module that increments an element pointer to the next value in the local array if the winning processor ID equals the processor ID for the local processor. | 12-11-2008 |
| 20080307195 | Parallel, Low-Latency Method for High-Performance Speculative Element Extraction From Distributed Arrays - The present invention provides a system and method for extracting elements from distributed arrays on a parallel processing system. The system includes a module that populates a result array with globally largest elements from the input, a module that generates a partition element, a module that counts the number of local elements greater than the partition and a module that determines the globally largest elements. The method for extracting elements from distributed arrays on a parallel processing system includes populating a result array with globally largest elements from the input, generating a partition element, counting the number of local elements greater than the partition and determining the globally largest elements. | 12-11-2008 |
| 20110219208 | MULTI-PETASCALE HIGHLY EFFICIENT PARALLEL SUPERCOMPUTER - A Multi-Petascale Highly Efficient Parallel Supercomputer of 100 petaOPS-scale computing, at decreased cost, power and footprint, and that allows for a maximum packaging density of processing nodes from an interconnect point of view. The Supercomputer exploits technological advances in VLSI that enables a computing model where many processors can be integrated into a single Application Specific Integrated Circuit (ASIC). Each ASIC computing node comprises a system-on-chip ASIC utilizing four or more processors integrated into one die, with each having full access to all system resources and enabling adaptive partitioning of the processors to functions such as compute or messaging I/O on an application by application basis, and preferably, enable adaptive partitioning of functions in accordance with various algorithmic phases within an application, or if I/O or other processors are underutilized, then can participate in computation or communication nodes are interconnected by a five dimensional torus network with DMA that optimally maximize the throughput of packet communications between nodes and minimize latency. | 09-08-2011 |
Brian Smith, Leduc CA
| Patent application number | Description | Published |
|---|---|---|
| 20080223506 | METHOD OF COLOUR REFURBISHING METAL DISPLAY FIXTURES - A method of colour refurbishing metal display fixtures. A first step involves printing on a display film an image of a desired colour finish. A second step involves securing the display film to components of a metal display fixture | 09-18-2008 |
Brian Smith, Ottawa CA
| Patent application number | Description | Published |
|---|---|---|
| 20080198747 | Efficient ethernet LAN with service level agreements - A method of controlling the flow of data packet traffic from a first point to at least two second point in an Ethernet telecommunications network having a multiplicity of nodes interconnected by multiple network links, comprises monitoring the level of utilization of a link between the first and second points, generating flow control messages representing the level of utilization and transmitting the control messages to the first point, and using the states represented in the flow control messages as factors in controlling the rate at which the packets are transmitted from the first point to the second point. A method of controlling the flow of data packet traffic through an Ethernet telecommunications network having a multiplicity of nodes interconnected by multiple network links, comprises receiving incoming data packet traffic from multiple customer connections at a first node for entry into the network via the first node, the first node having an ingress trunk, and limiting the rate at which the incoming data packets are admitted to the network via the ingress trunk. | 08-21-2008 |
Brian Smith, Chipping Nertin GB
| Patent application number | Description | Published |
|---|---|---|
| 20110226166 | OVERHEAD PROTECTION SYSTEM - A protective shelter is disclosed. The shelter may be sized to protect an existing, unhardened structure, and its contents. Or, the shelter may be sized to protect an individual or other objects of similar size. In either case, the shelter provides protection from blasts from explosive shells, rockets, and the like. The shelter has a support frame that supports a blast cover that is positioned above the object or objects to be protected. A burster screen is positioned above the blast cover and may be supported by the support frame. The burster screen serves to detonate incoming ordinance before the ordinance reaches the protected object or objects. The blast cover is strong enough to withstand the resulting shock from the detonated ordinance, and thus prevents damage to the protected object or objects located below the protective shelter. This invention may be used to retrofit existing, unhardened structures in areas where additional protection is needed. It also may be used as part of the design of new facilities, and offers the option to later remove the hardened, protective part of the structure if the threat level changes for the better. In the smaller, personnel-protection embodiment, the invention may be air dropped to remote locations and assembled by personnel in the field. | 09-22-2011 |
Brian Smith, Littleton, CO US
| Patent application number | Description | Published |
|---|---|---|
| 20110246638 | METHOD AND SYSTEM FOR PROVIDING MONITORING OF NETWORK ENVIRONMENT CHANGES - An approach is provided for monitoring network environment changes. A plurality of events relating to activation of one or more network elements are tracked, wherein the events include movement of cables for the network element and activities corresponding to verification of connections over the cables. Event information relating to the events are stored. The event information includes status information of the verification of the connections. Access is provided to the stored event information for presentation via a portal. | 10-06-2011 |
Brian Smith, Issaquah, WA US
| Patent application number | Description | Published |
|---|---|---|
| 20110289066 | SEARCH-HIGHLIGHTER SYSTEM AND METHOD - A text string may be captured when a user initiates a selection event in a web browser. In response to the selection event, the text string is derived from the selected element(s) in a rendered web page. The text string is automatically placed in a web-search text-entry field of the web browser without further instructions from the user. The user can modify the text string before querying a web-search engine. | 11-24-2011 |
Brian Smith, Milton, GA US
| Patent application number | Description | Published |
|---|---|---|
| 20120016698 | SYSTEMS AND METHODS FOR ALLOCATING INVENTORY - Computer-implemented systems and methods provide use an allocation process for allocating inventory items based on categories and attributes associated with the inventory items. The systems and methods allocate the inventory in accordance with a predefined hierarchy of the categories and attributes so as to effectively balance current reservations while accounting for overbook and/or retention criteria. The systems and methods facilitate the tracking of upgraded inventory reservations relative to non-upgraded inventory reservations. The inventory allocation can occur in real time and/or in accordance with a user-defined schedule. The inventory allocation can be substantially automated. | 01-19-2012 |
| 20120016699 | SYSTEMS AND METHODS FOR INVENTORY MANAGEMENT - Computer-implemented systems and methods provide for attribute-based inventory management. In the attribute-based inventory management, any one or more discrete attributes of an inventory item can be used to manage the inventory item. Management of the inventory item includes, for example, identifying the availability of the inventory item and identifying a rate to be charged for the inventory item. This attributes-based model for inventory management is highly flexible and scalable. | 01-19-2012 |
Brian Smith, Cambridge, MA US
| Patent application number | Description | Published |
|---|---|---|
| 20120086113 | FLEXIBLE CIRCUITS AND METHODS FOR MAKING THE SAME - Embodiments of the invention relate to a method for creating a flexible circuit, including defining a cavity in a top surface of a substrate before disposing a semiconductor chip within the cavity, such that a backside of the chip is disposed beneath the top surface of the substrate and above a bottom surface of the cavity. The method also includes forming a flexible connecting layer on the top surface of the substrate and extending over the chip. Other embodiments relate to a flexible circuit including a substrate defining a cavity in a top surface thereof. The cavity has encapsulant and a chip disposed therein, wherein a frontside of the chip is substantially coplanar with the top surface of the substrate. A flexible connecting layer is disposed on the top surface of the substrate and is partially supported by the substrate. | 04-12-2012 |
Brian Smith, San Diego, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20120135982 | 5HT2c RECEPTOR MODULATORS - The present invention relates to novel compounds of Formula (I): | 05-31-2012 |