| Patent application number | Description | Published |
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| 20090204797 | METHOD AND SYSTEM FOR MITIGATING LOOKAHEAD BRANCH PREDICTION LATENCY WITH BRANCH PRESENCE PREDICTION AT THE TIME OF INSTRUCTION FETCHING - System and method for mitigating lookahead branch prediction latency with branch presence prediction at the time of instruction fetching. An exemplary embodiment includes a method for mitigating lookahead branch prediction latency, the method including receiving an instruction address in an instruction cache for fetching instructions in the microprocessor pipeline, receiving the instruction address in a branch presence predictor coupled to the microprocessor pipeline, and releasing instructions extracted from the instruction cache after determining that a branch prediction is available or unlikely to occur for instructions identified as potential predictable branches by the branch presence prediction. | 08-13-2009 |
| 20090204799 | METHOD AND SYSTEM FOR REDUCING BRANCH PREDICTION LATENCY USING A BRANCH TARGET BUFFER WITH MOST RECENTLY USED COLUMN PREDICTION - System and method for reducing branch prediction latency using a branch target buffer with most recently used column prediction. An exemplary embodiment includes a method for reducing branch prediction latency, the method including reading most-recently-used information from a most-recently-used table associated with the branch target buffer where each most-recently-used entry corresponds to one or more branch target buffer rows and specifies the ordering from least-recently-used to most-recently-used of the associated branch target buffer columns, selecting a row from the branch target buffer and simultaneously selecting the associated entry from the most-recently-used table and speculating that there is a prediction in the most recently used column of the plurality of columns from the selected row from the branch target buffer while determining whether there is a prediction and which column contains the prediction. | 08-13-2009 |
| 20090210661 | METHOD, SYSTEM AND COMPUTER PROGRAM PRODUCT FOR AN IMPLICIT PREDICTED RETURN FROM A PREDICTED SUBROUTINE - A method, system and computer program product for performing an implicit predicted return from a predicted subroutine are provided. The system includes a branch history table/branch target buffer (BHT/BTB) to hold branch information, including a target address of a predicted subroutine and a branch type. The system also includes instruction buffers, and instruction fetch controls to perform a method including fetching a branch instruction at a branch address and a return-point instruction. The method also includes receiving the target address and the branch type, and fetching a fixed number of instructions in response to the branch type. The method further includes referencing the return-point instruction within the instruction buffers such that the return-point instruction is available upon completing the fetching of the fixed number of instructions absent a re-fetch of the return-point instruction. | 08-20-2009 |
| 20090210684 | METHODS, SYSTEMS, AND COMPUTER PROGRAM PRODUCTS FOR RECOVERING FROM BRANCH PREDICTION LATENCY - A branch prediction algorithm is used to generate a prediction of whether or not a branch will be taken. One or more instructions are fetched such that, for each of the fetched instructions, the prediction initiates a fetch of an instruction at a predicted target of the branch. A test is performed to ascertain whether or not the prediction was generated late relative to the fetched instructions, so that if the branch is later detected as mispredicted, that detection can be correlated to the late prediction. When the prediction is generated late relative to the fetched instructions, a latent prediction is selected by utilizing a fetching initiated by the latent prediction such that a new fetch is not started. | 08-20-2009 |
| 20090210686 | METHOD AND SYSTEM FOR PURGING PATTERN HISTORY TABLES AS A FUNCTION OF GLOBAL ACCURACY IN A STATE MACHINE-BASED FILTERED GSHARE BRANCH PREDICTOR - A method, system and computer product for purging pattern history tables as a function of global accuracy in a state machine-based filter gshare branch predictor. An exemplary embodiment includes a method including storing a plurality of encountered branch instructions in the branch history table, indexing the branch history table by a branch instruction address, modifying an entry of the branch history table, indexing the pattern history table, selecting at least one of a branch history entry and a pattern history table entry as a prediction for the branch instruction, wherein the pattern history table entry is selected as the prediction for the branch instruction in response to the branch history entry being in a state specifying to use the pattern history table entry, comparing a pattern history table accuracy to an accuracy threshold, and in response to the pattern history table accuracy falling below the accuracy threshold, purging the PHT. | 08-20-2009 |
| 20090210730 | METHOD AND SYSTEM FOR POWER CONSERVATION IN A HIERARCHICAL BRANCH PREDICTOR - A method and system for power conservation in a hierarchical branch predictor system are provided. The method includes addressing multiple branch predictors, each of the branch predictors having various sizes of hierarchical storage and storing information about previously encountered branch instructions. In response to receiving a first branch prediction from one of the branch predictors, the method includes comparing the first branch prediction with previously stored branch predictions to determine the existence of a branch prediction loop, the branch prediction loop including a sequence of branch predictions that repeat as long as constituent predictions of the branches remain unchanged. Upon determining that a branch prediction loop exists, the method includes associating the branch prediction loop with the branch predictors that provided each branch prediction, and activating power saving to the branch predictors that are not associated with the branch prediction loop. | 08-20-2009 |
| 20090210775 | METHOD AND SYSTEM FOR INSTRUCTION ADDRESS PARITY COMPARISON - A method and system for instruction address parity comparison are provided. The method includes calculating an instruction address parity value for an instruction, and distributing the instruction address parity value to one or more functional units in processing circuitry. The method also includes receiving the distributed instruction address parity value from the one or more functional units, and calculating a completing instruction address (CIA) parity value associated with completing the instruction. The method further includes generating an error indicator in response to a mismatch between the received instruction address parity value and the CIA parity value. | 08-20-2009 |
| 20090216952 | METHOD, SYSTEM, AND COMPUTER PROGRAM PRODUCT FOR MANAGING CACHE MEMORY - A method for managing cache memory including receiving an instruction fetch for an instruction stream in a cache memory, wherein the instruction fetch includes an instruction fetch reference tag for the instruction stream and the instruction stream is at least partially included within a cache line, comparing the instruction fetch reference tag to a previous instruction fetch reference tag, maintaining a cache replacement status of the cache line if the instruction fetch reference tag is the same as the previous instruction fetch reference tag, and upgrading the cache replacement status of the cache line if the instruction fetch reference tag is different from the previous instruction fetch reference tag, whereby the cache replacement status of the cache line is upgraded if the instruction stream is independently fetched more than once. A corresponding system and computer program product. | 08-27-2009 |
| 20090217002 | SYSTEM AND METHOD FOR PROVIDING ASYNCHRONOUS DYNAMIC MILLICODE ENTRY PREDICTION - A system and method for asynchronous dynamic millicode entry prediction in a processor are provided. The system includes a branch target buffer (BTB) to hold branch information. The branch information includes: a branch type indicating that the branch represents a millicode entry (mcentry) instruction targeting a millicode subroutine, and an instruction length code (ILC) associated with the mcentry instruction. The system also includes search logic to perform a method. The method includes locating a branch address in the BTB for the mcentry instruction targeting the millicode subroutine, and determining a return address to return from the millicode subroutine as a function of the an instruction address of the mcentry instruction and the ILC. The system further includes instruction fetch controls to fetch instructions of the millicode subroutine asynchronous to the search logic. The search logic may also operate asynchronous with respect to an instruction decode unit. | 08-27-2009 |
| 20090217003 | METHOD, SYSTEM, AND COMPUTER PROGRAM PRODUCT FOR REDUCING CACHE MEMORY POLLUTION - A method for reducing cache memory pollution including fetching an instruction stream from a cache line, preventing a fetching for the instruction stream from a sequential cache line, searching for a next predicted taken branch instruction, determining whether a length of the instruction stream extends beyond a length of the cache line based on the next predicted taken branch instruction, continuing preventing the fetching for the instruction stream from the sequential cache line if the length of the instruction stream does not extend beyond the length of the cache line, and allowing the fetching for the instruction stream from the sequential cache line if the length of the instruction stream extends beyond the length of the cache line, whereby the fetching from the sequential cache line and a resulting polluting of a cache memory that stores the instruction stream is minimized. A corresponding system and computer program product. | 08-27-2009 |
| 20090217015 | SYSTEM AND METHOD FOR CONTROLLING RESTARTING OF INSTRUCTION FETCHING USING SPECULATIVE ADDRESS COMPUTATIONS - A system and method for controlling restarting of instruction fetching using speculative address computations in a processor are provided. The system includes a predicted target queue to hold branch prediction logic (BPL) generated target address values. The system also includes target selection logic including a recycle queue. The target selection logic selects a saved branch target value between a previously speculatively calculated branch target value from the recycle queue and an address value from the predicted target queue. The system further includes a compare block to identify a wrong target in response to a mismatch between the saved branch target value and a current calculated branch target, where instruction fetching is restarted in response to the wrong target. | 08-27-2009 |
| 20090217016 | SYSTEM AND METHOD FOR SEARCH AREA CONFINED BRANCH PREDICTION - A system and method for performing search area confined branch prediction in a processor are provided. The system includes a branch target buffer (BTB) to hold branch information for branch prediction, where the branch information includes a branch address. The system also includes search logic for searching the BTB to locate a branch address. The system additionally includes throttle logic to stop searching the BTB in response to reaching a predefined search limit. | 08-27-2009 |
| 20090217017 | METHOD, SYSTEM AND COMPUTER PROGRAM PRODUCT FOR MINIMIZING BRANCH PREDICTION LATENCY - A method, system, and computer program product for minimizing branch prediction latency in a pipelined computer processing environment are provided. The method includes detecting a branch loop utilizing branch instruction addresses and corresponding target addresses stored in a branch target buffer (BTB). The method also includes fetching the branch loop into a pre-decode instruction buffer and qualifying the branch loop for loop lockdown. The method further includes locking an instruction stream that forms the branch loop in the pre-decode instruction buffer and processing qualified branch loop instructions from the buffer and powering down instruction fetching and branch prediction logic (BPL) associated with the BTB. | 08-27-2009 |
| 20090240929 | METHOD, SYSTEM AND COMPUTER PROGRAM PRODUCT FOR REDUCED OVERHEAD ADDRESS MODE CHANGE MANAGEMENT IN A PIPELINED, RECYLING MICROPROCESSOR - A method, system, and computer program product for reduced overhead address mode change management in a pipelined, recycling microprocessor are provided. The recycling microprocessor includes logic executing thereon. The microprocessor also includes an instruction fetch unit (IFU) supporting computation of address adds in selected address modes and reporting non-equal comparison of the computation to the logic. The microprocessor further includes a fixed point unit determining whether the mode has changed and reporting changes to the logic. Upon determining the comparison yields an equal result but the mode has changed, a recycle event is triggered to ensure subsequent ofetches are relaunched in the correct mode and that no execution writebacks occur from work performed in an incorrect mode. For comparisons yielding a non-equal result and a changed mode, the logic clears bits set in response to the determinations, and a serialization event is taken to reset a corresponding pipeline for operation in the correct mode. | 09-24-2009 |
| 20090240977 | METHOD, SYSTEM AND COMPUTER PROGRAM PRODUCT FOR HARD ERROR DETECTION - An error detection system is provided. The system includes a data array that includes one or more data entries. A copy datastore selectively stores a copy of a first single data entry of the data array. An index generator selectively increments an index that references the data array. A first comparator compares the copy with a second single data entry from the data array based on the index. An error generator generates an error signal based on a result from the first comparator. | 09-24-2009 |
| 20090313462 | METHODS INVOLVING BRANCH PREDICTION - A method for branch prediction, the method comprising, receiving a load instruction including a first data location in a first memory area, retrieving data including a branch address and a target address from the first data location data location, and saving the data in a branch prediction memory. | 12-17-2009 |
| 20100287358 | Branch Prediction Path Instruction - A method for branch prediction, the method comprising, receiving a branch wrong guess instruction having a branch wrong guess instruction address and data including an opcode and a branch target address, determining whether the branch wrong guess instruction was predicted by a branch prediction mechanism, sending the branch wrong guess instruction to an execution unit responsive to determining that the branch wrong guess instruction was predicted by the branch prediction mechanism, and receiving and decoding instructions at the branch target address. | 11-11-2010 |
