| Patent application number | Description | Published |
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| 20080246453 | POWER SUPPLY SYSTEM USING DELAY LINES IN REGULATOR TOPOLOGY TO REDUCE INPUT RIPPLE VOLTAGE - A power supply system for reducing input ripple voltage, the system including: a first regulator having at least two inputs, one input being a voltage input pin and another input being a synchronization pin; a second regulator having at least two inputs, one input being a voltage input pin and another input being a synchronization pin; a Nth regulator having at least two inputs, one input being a voltage input pin and another input being a synchronization pin; wherein outputs of the first regulator, second regulator, and Nth regulator are connected to a single power bus or correspondingly to separate power buses; a first delay connected to the synchronization pin of the second regulator; a second delay connected to the synchronization pin of the Nth regulator; wherein the first delay and the second delay have different delays configured for enabling the first regulator, second regulator, and the Nth regulator to operate out of phase; and a master clock for providing timing control to the first and second delay. | 10-09-2008 |
| 20080259514 | METHOD, APPARATUS, AND COMPUTER PROGRAM PRODUCT FOR DETECTING EXCESS CURRENT FLOW IN A PLUGGABLE COMPONENT - Detecting excess current flow in a pluggable component is performed by completing a first current supply path between a power source and a pluggable component, and subsequently completing a second current supply path in parallel with the first current supply path. The first and second current supply paths form a current divider for supplying the pluggable component with electrical power from the power source. The first current supply path includes a current sensing mechanism for sensing current consumption of the pluggable component. The sensed current consumption is used to provide excess current detection for the pluggable component. | 10-23-2008 |
| 20080304489 | APPARATUS AND METHOD TO SET THE SIGNALING RATE OF A NETWORK DISPOSED WITHIN AN INFORMATION STORAGE AND RETRIEVAL SYSTEM - A method is disclosed to set the speed of a network. The method supplies a network interconnected with a system controller and a plurality of switch domains, where each of those plurality of switch domains comprises one or more information storage devices and a switch domain controller, and sets by each of the plurality of switch domains a signaling rate for that switch domain. The method queries in-band by the system controller each of the plurality of switch domains for that switch domain's signaling rate, and provides in-band by each of the plurality of switch domains the signaling rate for that switch domain. The method provides in-band by the system controller to each of the plurality of switch domains a first speed selection command specifying a first network speed, and resets by each of the plurality of switch domains the signaling rate for that switch domain to the first network speed. | 12-11-2008 |
| 20080307185 | APPARATUS AND METHOD TO SET SIGNAL COMPENSATION SETTINGS FOR A DATA STORAGE DEVICE - A method is disclosed to set signal compensation settings for a data storage device comprising a first port and a second port, where that first port is interconnected to a first switch via a first communication pathway having a predetermined first length. The method determines first signal compensation settings based upon the first length. | 12-11-2008 |
| 20090235130 | TEST PATTERN CUSTOMIZATION OF HIGH SPEED SAS NETWORKS IN A MANUFACTURING TEST SYSTEM - A method for testing a high-speed serial interface, comprising: generating a customized stress test pattern configured to violate an 8bit/10bit-encoding scheme into an expander, the customized stress test pattern is configured to stress the high-speed serial interface beyond marginal limits resulting in less testing to force errors within the high-speed serial interface; transmitting the customized stress test pattern from a transmit port of a first serializer/deserializer device of the high-speed serial interface; and monitoring a receive port of a second serializer/deserializer device to detect errors within the high-speed serial interface. | 09-17-2009 |
| 20090254772 | Extending and Scavenging Super-Capacitor Capacity - A memory system has mechanisms for scavenging capacity of a super capacitor by removing, or reducing, system load from the super capacitor when the super capacitor voltage decays below a low threshold. The mechanisms then restore the system load to the super capacitor when the super capacitor voltage ramps back above a high threshold. A controller may reduce system load by placing a volatile memory system in a standby state and disabling a field effect transistor to remove power from a non-volatile memory system. A controller may adjust the high threshold and/or a low threshold by setting a digitally controlled potentiometer in a threshold detect circuit via an I | 10-08-2009 |
| 20090323452 | Dual Mode Memory System for Reducing Power Requirements During Memory Backup Transition - A controller of a memory system is configured to reduce power requirements during memory backup transition. When transitioning to backup mode, the memory system controller performs a number of power saving techniques. The controller may change a number of configuration settings in the volatile memory system, such as reducing output driver strength, increasing differential impedance, increasing on-die termination, disabling receiver input circuitry, and disconnecting the termination voltage network. The controller may also assert a hard reset to the storage controller system to significantly reduce the load and allow the voltage regulator to continue to provide power to the memory system for a longer period of time. | 12-31-2009 |
| 20090327578 | Flash Sector Seeding to Reduce Program Times - A non-volatile flash memory comprises a plurality of non-volatile memories where a first non-volatile memory is pre-programmed (erased) with all ones, and at least a second non-volatile memory is pre-programmed with a seed value that takes advantage of the reduced programming time for less than six zeros. When writing (programming) a data byte, the memory system looks up the data byte in one or more seed tables to determine a portion of non-volatile memory to which the memory system may write the data byte with a reduced programming time. The memory system then records the location of the data byte in an address translation table so the data byte may be accessed. | 12-31-2009 |
| 20100008409 | METHOD FOR CLOCK JITTER STRESS MARGINING OF HIGH SPEED INTERFACES - A method for clock jitter stress margining of high speed interfaces including generating a jittered clock signal via a clock signal generator of a high speed interface controller card, inputting the jittered clock signal to a control input of a looped-back port of the high speed interface controller card, inputting a test pattern signal to the looped-back port generated from a logic circuitry of the high speed interface controller card, receiving the test pattern signal to the logic circuitry from the looped-back port via the transmitter to the receiver, monitoring a bit error rate of the looped-back port by comparing the received test pattern signal to the inputted test pattern signal, and outputting a fail indication signal if the bit error rate is within a fail threshold. | 01-14-2010 |
| 20100011261 | Verifying Data Integrity of a Non-Volatile Memory System during Data Caching Process - To ensure integrity of non-volatile flash, the controller programs the non-volatile memories with background test patterns and verifies the non-volatile memories during power on self test (POST) operation. In conjunction with verifying the non-volatile memories, the controller may routinely run diagnostics and report status to the storage controller. As part of the storage controller power up routines, the storage controller issues a POST command to the controller via an I | 01-14-2010 |
| 20100052625 | In Situ Verification of Capacitive Power Support - A mechanism for in situ verification of capacitive power support is provided. A memory system uses a super capacitor to support a voltage rail when input power is lost or interrupted. The voltage discharge curve is a function of load and capacitance of the component. By stepping the regulated power supply to a lower output within the voltage range and recording voltage and current draw at the super capacitor as it discharges to the new regulator output voltage, the super capacitor holdup capability can be tested. | 03-04-2010 |
| 20110113279 | Method Apparatus and System for a Redundant and Fault Tolerant Solid State Disk - A redundant and fault tolerant solid state disk (SSDC) includes a determination module configured to identify a first SSDC configured to connect to a flash array and a second SSDC configured to connect to the flash array. A capture module is configured to capture a copy of an I/O request received by the first SSDC from a port of a dual port connector, and/or capture a copy of an I/O request received by the second SSDC from a port of the dual port connector, and identify a write I/O request from the I/O request. A detection module is configured to detect a failure in the first SSDC. A management module is configured to manage access to a flash array by the first SSDC and the second SSDC. An error recovery and failover module is configured to automatically reassign work from the first SSDC to the second SSDC. | 05-12-2011 |
