Patent application number | Description | Published |
20130343181 | SYSTEMS AND METHODS OF DATA PROCESSING USING AN FPGA-IMPLEMENTED HASH FUNCTION - A method for processing data packets in a computer system may include receiving a data packet at a configurable logic device (e.g., an FPGA), each packet including header information regarding the data packet, the configurable logic device automatically identifying particular information elements in the header information of the data packet, the configurable logic device automatically executing a hash function programmed on the configurable logic device to calculate a hash value for the data packet based on the particular information elements, and processing the data packet based on the calculated hash value for the data packet. The calculate hash value may be used for various purposes, e.g., routing and/or load balancing of traffic across multiple interfaces. The configurable logic device may be able to execute the hash function at line rate, thus freeing up processor cycles in one or more related processors. | 12-26-2013 |
20130343207 | DYNAMIC LATENCY ANALYSIS SYSTEM - An automated method for analyzing a plurality of network messages received by a network testing device is disclosed. The method may comprise, during a current window of time, receiving from a target network device a network message associated with an original network message determining a latency value for the received network message comparing the determined latency value with the threshold latency value; and incrementing either the first counter or the second counter based on the comparison of the determined latency value with a threshold latency value. The method may further comprise, at the end of the current window of time, storing the first and second counter values resulting from the analysis of the plurality of original network messages. | 12-26-2013 |
20130343377 | HASH-BASED PACKET DISTRIBUTION IN A COMPUTER SYSTEM - A method for distributing packets across multiple parallel interfaces between a first instruction executing device and a second instruction executing device may include: the first instruction executing device receiving a stream of data packets, each data packet including header information regarding that data packet; and for each data packet, the first instruction executing device executing instructions to identify one or more particular information elements in the data packet; execute a hash function to the one or more particular information elements to calculate a hash value for the data packet; select a particular one of the multiple parallel communication interfaces based on the calculated hash value for the data packet; and forward the data packet to the second instruction executing device via the selected communication interface. Such method may provide traffic load balancing across the multiple parallel interfaces. | 12-26-2013 |
20130343379 | ETHERNET-BASED INTERNAL DEVICE MANAGEMENT - A method of communicating between devices within a card in a computing system comprises sending a command network packet from a first instruction executing device to a second instruction executing device via an Ethernet network, wherein the command network packet contains an instruction to be executed on the second instruction executing device, and receiving a responsive network packet sent from the second instruction executing device to the first instruction executing device via the Ethernet network, wherein the responsive network packet indicates a result of the instruction. | 12-26-2013 |
20130343380 | FLEXIBLE PORT BINDING FOR CONTROL PROCESSOR - A method of flexibly binding physical network interface ports to a processor in a network testing system comprises generating an egress network packet with a prepend header at a processor, wherein the prepend header specifies a particular physical network interface through which the egress network packet should be transmitted, transmitting the prepended network packet to a configurable logic device (CLD), routing the prepended network packet to the specified physical network interface. | 12-26-2013 |
20130343387 | HIGH-SPEED CLD-BASED INTERNAL PACKET ROUTING - A method of routing internal network traffic within a computing system comprises receiving a network packet at a configurable logic device (CLD), parsing the network packet to obtain a destination address, searching a predetermined range of a routing table wherein each row of the routing table specifies a range of possible destination addresses and routing information, identifying a matching row of the routing table wherein the destination address falls within the range of possible destination addresses of the matching row, and routing the packet according to the routing information. | 12-26-2013 |
20130343388 | BINDING OF NETWORK FLOWS TO PROCESS THREADS - A method of routing internal network traffic within a computing system, comprises receiving a network packet at a configurable logic device (CLD), parsing the network packet to obtain a source address and a destination address, searching a predetermined range of a routing table wherein each row of the routing table specifies a range of possible destination addresses and a thread group identifier, identifying a matching row of the routing table wherein the destination address falls within the range of possible destination addresses of the matching row, calculating a hash value based at least in part on the source and destination addresses, and determining a thread identifier based at least in part on the hash value and the thread group identifier. | 12-26-2013 |
20130343407 | HIGH-SPEED CLD-BASED TCP ASSEMBLY OFFLOAD - A method offloading data intensive tasks from a processor comprises receiving at a configurable logic device (CLD) a network packet, parsing the network packet to determine that the packet is a TCP segment, searching a partially assembled packet table to locate an associated partially assembled packet data structure, inserting the network packet into the associated partially assembled packet data structure, recognizing that the partially assembled packet data structure contains every segment produced from an original TCP packet, assembling a fully assembled TCP packet from the data in the partially assembled packet data structure, and transmitting the fully assembled TCP packet to a processor in the same computer system as the CLD. | 12-26-2013 |
20130343408 | HIGH-SPEED CLD-BASED TCP SEGMENTATION OFFLOAD - A method of offloading data intensive tasks from a processor, comprises, at a processor, preparing a TCP packet comprising a TCP header and a data payload, transmitting the TCP packet to a configurable logic device (CLD); and at the CLD, receiving the TCP packet, generating set of TCP segment packets containing, a copy of the TCP header, an incrementing segment sequence identifier, and a portion of the data payload, and transmitting the set of TCP segment packets on an external network interface. | 12-26-2013 |
20130346415 | SYSTEMS AND METHODS MULTI-KEY ACCESS TO DATA - A computer-implemented method of storing data for fast lookup comprises forming a first and a second array of pointers, forming a record to store, the record comprising fields for, a first list pointer, a second list pointer, which is not the first field in the record, a first key, and a second key. The method further comprises determining a first index based at least in part the first key, setting the value of the pointer at the first index in the first array to the location of the first pointer field of the record, determining a second index based at least in part the second key, and setting the value of the pointer at the second index in the second array to the location of the second pointer field of the record. | 12-26-2013 |
20130346628 | DYNAMICALLY ASSIGNED MAC ADDRESSES FOR DEVICES IN A COMPUTING SYSTEM - A method for assigning Media Access Control (MAC) addresses to devices of a computing system includes: for each of a plurality of devices of the computing system, determining particular information regarding that device during a boot process for that device, and dynamically generating a MAC address for each device that indicates the determined particular information regarding that device. The particular information regarding each device may include, for example, information regarding the location of the device in the system (e.g., slot information), device type information, device number information, etc. | 12-26-2013 |
20130346667 | SERIAL PORT ACCESS SYSTEM AND METHOD IN A COMPUTING SYSTEM - A multi-card system includes a card having a plurality of serial port devices, an inter-card serial bus connection configured for connection to an inter-card serial bus, and an intra-card and inter-card serial port access system. The serial port access system may include a switch configured to provide switchable serial connections between any of the devices on the card, and an inter-card signaling system to communicate switching instructions to other cards. A serial connection can be enabled between a particular device on the card and a target device on another card by controlling the switch to connect the particular device with the inter-card serial bus connection, and sending an instruction to the other card via the inter-card signaling system to enable a connection between the target device and the inter-card serial bus, such that a serial connection is provided between the particular device and the target device via the inter-card serial bus. | 12-26-2013 |
20130346700 | SYSTEMS AND METHODS FOR MANAGING MEMORY - A method of accessing data in a shared-memory, parallel-processing computing system, comprises, on a first processing unit, receiving a reference for a data structure stored in a memory and a first value of a generation attribute associated with the data structure, waiting to receive an exclusive lock on the data structure, obtaining an exclusive lock on the data structure, receiving a second value of a second generation attribute associated with the data structure; and accessing the data structure only if the first generation attribute value and the second generation attribute value are identical. | 12-26-2013 |
20130346719 | SYSTEMS AND METHODS FOR EFFICIENT MEMORY ACCESS - A computer-implemented method of accessing data comprises resetting the value of a register of a first processing core of a multi-core processor, copying the bits of a compressed pointer into the lowest order bits of the register, left shifting the register a predetermined number of bits, and executing on the first processing core a first instruction referencing memory at a virtual address specified by the register. | 12-26-2013 |
20130346736 | SYSTEMS AND METHOD FOR BOOTING DEVICES IN A MULTIPLE-CARD COMPUTING SYSTEM - A method for booting devices in a multi-card computing system comprising a plurality of cards connected to a shared backplane may include: dynamically generating a Media Access Control (MAC) addresses for at least some of the devices in the computing system, the dynamically generated MAC address for each device including information regarding the location of that device within the multi-card computing system; a boot management system receiving a boot-related information request from a particular device in the multi-card system, the boot-related information request comprising a request for particular boot-related information for facilitating a boot process for the requesting device, and including the MAC address of the requesting device; and the boot management system determining whether to send a response to the requesting device with the requested boot-related information based at least on the information in the MAC address regarding the location of the requesting device within the multi-card computing system. | 12-26-2013 |
20130346756 | BRANDING A COMMODITY DRIVE - A computer implemented method for branding a commodity drive may include reading a unique identifier from a drive, partitioning the drive into a first partition and a second partition, combining the unique identifier with a secret to form an encoded value, and writing the encoded value to the first partition. | 12-26-2013 |
20130346987 | SYSTEMS AND METHODS FOR DISTRIBUTING TASKS AND/OR PROCESSING RECOURCES IN A SYSTEM - A method is provided for managing the execution of tasks by a system having multiple processors, each having multiple types of resources. The method may include receiving from a user a task configuration specifying one or more performance parameters for a proposed task, automatically determining for each type of resource a quantity of that resource corresponding to the performance parameters for the proposed task, automatically determining for each processor a quantity of each type of resource available to that processor, automatically comparing for processor (a) the quantity of each type of resource available to that processor with (b) the quantity of each type of resource corresponding to the performance parameters for the proposed task, automatically determining based on the comparisons whether any processor has capacity to perform the proposed task, and automatically determining whether to perform the proposed task based at least on whether any processor has capacity to perform the task. | 12-26-2013 |