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Brent A. Anderson
Brent A. Anderson, Essex Junction, VT US
| Patent application number | Description | Published |
|---|---|---|
| 20110037104 | VERTICAL SPACER FORMING AND RELATED TRANSISTOR - Methods include, for example, forming a vertically disposed active region on a substrate; forming a first gate over a portion of the vertically disposed active region; forming a dielectric over the portion; exposing an upper surface of the first gate; forming a second gate over the upper surface; and forming a spacer pocket region between the vertically disposed active region, the first gate and the dielectric, wherein the spacer pocket region is self-aligned to a lower surface of the second gate and has a substantially uniform thickness from an upper to a lower extent thereof. | 02-17-2011 |
| 20110049724 | BEOL INTERCONNECT STRUCTURES AND RELATED FABRICATION METHODS - Methods for forming voids in BEOL interconnect structures and BEOL interconnect structures. The methods include forming a temporary feature on a top surface of a first dielectric layer and depositing a second dielectric layer on the top surface of the first dielectric layer. The temporary feature is removed from the second dielectric layer to define a void in the second dielectric layer that is laterally adjacent to a conductive feature in the second dielectric layer. The void operates to reduce the effective dielectric constant of the second dielectric layer, which reduces parasitic capacitance between the conductive feature and other conductors in the BEOL interconnect structure. | 03-03-2011 |
| 20110068398 | TRENCH-GENERATED TRANSISTOR STRUCTURES, FABRICATION METHODS, DEVICE STRUCTURES, AND DESIGN STRUCTURES - Trench-generated transistor structures, methods for fabricating transistors using a trench defined in a semiconductor-on-insulator (SOI) wafer, design structures for a trench-generated transistor, and other trench-generated device structures. The source and drain of the transistor are defined by doped regions in the semiconductor material of the handle substrate of the SOI wafer. The gate electrode may be defined from the semiconductor layer of the SOI wafer, which is separated from the handle wafer by an insulating layer. Alternatively, the gate electrode may be defined as a conventional gate stack on a shallow trench isolation region in the semiconductor layer or as a conventional gate stack in one of the BEOL interconnect levels. | 03-24-2011 |
Brent A. Anderson, Jerihco, VT US
| Patent application number | Description | Published |
|---|---|---|
| 20090206374 | MULTI-FIN MULTI-GATE FIELD EFFECT TRANSISTOR WITH TAILORED DRIVE CURRENT - Disclosed are embodiments of an improved multi-gated field effect transistor (MUGFET) structure and method of forming the MUGFET structure so that it exhibits a more tailored drive current. Specifically, the MUGFET incorporates multiple semiconductor fins in order to increase effective channel width of the device and, thereby, to increase the drive current of the device. Additionally, the MUGFET incorporates a gate structure having different sections with different physical dimensions relative to the semiconductor fins in order to more finely tune device drive current (i.e., to achieve a specific drive current). Optionally, the MUGFET also incorporates semiconductor fins with differing widths in order to minimize leakage current caused by increases in drive current. | 08-20-2009 |
| 20090209074 | METHOD OF FORMING A MULTI-FIN MULTI-GATE FIELD EFFECT TRANSISTOR WITH TAILORED DRIVE CURRENT - Disclosed are embodiments of an improved multi-gated field effect transistor (MUGFET) structure and method of forming the MUGFET structure so that it exhibits a more tailored drive current. Specifically, the MUGFET incorporates multiple semiconductor fins in order to increase effective channel width of the device and, thereby, to increase the drive current of the device. Additionally, the MUGFET incorporates a gate structure having different sections with different physical dimensions relative to the semiconductor fins in order to more finely tune device drive current (i.e., to achieve a specific drive current). Optionally, the MUGFET also incorporates semiconductor fins with differing widths in order to minimize leakage current caused by increases in drive current. | 08-20-2009 |
Brent A. Anderson, Hericho, VT US
| Patent application number | Description | Published |
|---|---|---|
| 20090140328 | Bridged Gate FinFet - In a fin-type field effect transistor (FinFET) structure, a gate strap is positioned on the top of a gate conductor and runs along the gate conductor. The top of the gate strap is positioned a greater height above the top surface of the substrate than the top of the fin cap. The gate strap is conformal and, therefore, the top of the portion of the gate strap that crosses the fin cap has a greater height above the top surface of the substrate than top portions of other regions of the gate strap. Further, the material of the gate strap can have a different work function than a material of the gate conductor. | 06-04-2009 |
Brent A. Anderson, Lincoln Park, NJ US
| Patent application number | Description | Published |
|---|---|---|
| 20080317891 | Edible Products Having A High Cocoa Polyphenol Content and Improved Flavor and The Milled Cocoa Extracts Used Therein - Milling dry extracts containing cocoa polyphenols (CPs) to reduce the particle size improves the flavor of edible products (e.g., foods, medical foods, nutritional supplements, and pharmaceuticals) or additives containing the milled cocoa extracts. The products, e.g., chocolates, are less astringent and less bitter. The mean particle size after milling is less than about 15 microns, preferably less than about 10 microns, and most preferably less than about 5 microns. The total CP content of the milled extracts is at least about 300 milligrams and preferably about 300 to about 700 milligrams per gram of milled extract. The additives consist essentially of (i) the milled high CP cocoa extract and (ii) a fat (e.g., cocoa butter), an oil (e.g., vegetable oil), or a syrup (e.g., corn syrup). | 12-25-2008 |
Brent A. Anderson, Jerhico, VT US
| Patent application number | Description | Published |
|---|---|---|
| 20080284021 | Method for FEOL and BEOL Wiring - A method for forming a conductive structure of sub-lithographic dimension suitable for FEOL and BEOL semiconductor fabrication applications. The method includes forming a topographic feature of silicon-containing material on a substrate; forming a dielectric cap on the topographic feature; applying a mask structure to expose a pattern on a sidewall of the topographic feature, the exposed pattern corresponding to a conductive structure to be formed; depositing a metal at the exposed portions of the sidewall and forming one or more metal silicide conductive structures at the exposed sidewall portions; removing the dielectric cap layer; and removing the silicon-containing topographic feature. The result is the formation of one or more metal silicide conductor structures formed for a single lithographically defined feature. In example embodiments, the formed metal silicide conductive structures have a high aspect ratio, e.g., ranging from 1:1 to 20:1 (height to width dimension). | 11-20-2008 |