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Brar

Amanpreet Singh Brar, Punjab IN

Patent application numberDescriptionPublished
20080317347Rendering engine test system - A system to compare a reference image of a text character, word or phrase with another image of the character, word or phrase that was rendered by a text rendering engine. Differences between the reference image and the rendered image may be recorded for subsequent analysis. Performance of a text rendering engine producing text according to typographical rules applicable to a natural language can be evaluated by one with no knowledge or ability to read the natural language.12-25-2008

Berinder Brar, Newbury Park, CA US

Patent application numberDescriptionPublished
20100219449METHOD AND APPARATUS FOR HETEROJUNCTION BARRIER DIODE DETECTOR FOR ULTRAHIGH SENSITIVITY - The disclosure relates to a zero-bias heterojunction diode detector with varying impedance. The detector includes a substrate supporting a Schottky structure and an Ohmic contact layer. A metallic contact layer is formed over the Ohmic layer. The Schottky structure comprises a plurality of barrier layers and each of the plurality of barriers layers includes a first material and a second material. In one embodiment, the composition percentage of the second material in each of the barrier layers increases among the plurality of barrier layers from the substrate to the metal layer in order to provide a graded periodicity for the Schottky structure.09-02-2010
20110018034HETEROGENEOUS INTEGRATION OF LOW NOISE AMPLIFIERS WITH POWER AMPLIFIERS OR SWITCHES - A transistor heterogeneously integrating a power amplifier or switch with a low-noise amplifier having a substrate wafer selected from a group consisting of Gallium Arsenide (GaAs), Indium Phosphate (InP) and Gallium Antimonide (GaSb), the substrate having a first end and a second end, a conducting layer above the first end of the substrate, an isolation implant providing lateral isolation in the conducting layer, a first active layer deposited above the conducting layer and configured for the low-noise amplifier, and a buffer layer deposited above the conducting layer and configured for the low-noise amplifier.01-27-2011
20110031531PROCESS FOR FORMING LOW DEFECT DENSITY HETEROJUNCTIONS - A method for forming a low defect density heterojunction between a first and a second compound, the first and second compounds each includes a group III element combined with a group V element in the periodic table, the method includes the steps of introducing in the deposition chamber the flux of the group III element for the first compound at substantially the same time while introducing in the deposition chamber a flux of the group V element for the second compound, stopping the flux of the group III element for the first compound after a first predetermined time period, stopping the flux of the group V element for the first compound after a second predetermined time period, and introducing in the deposition chamber a flux of the group III element the group V element for the second compound.02-10-2011
20110143518HETEROGENEOUS INTEGRATION OF LOW NOISE AMPLIFIERS WITH POWER AMPLIFIERS OR SWITCHES - A transistor heterogeneously integrating a power amplifier or switch with a low-noise amplifier having a substrate wafer selected from a group consisting of Gallium Arsenide (GaAs), Indium Phosphate (InP) and Gallium Antimonide (GaSb), the substrate having a first end and a second end, a conducting layer above the first end of the substrate, an isolation implant providing lateral isolation in the conducting layer, a first active layer deposited above the conducting layer and configured for the low-noise amplifier, and a buffer layer deposited above the conducting layer and configured for the low-noise amplifier.06-16-2011
20110220967PROCESS FOR FORMING LOW DEFECT DENSITY HETEROJUNCTIONS - A method for forming a low defect density heterojunction between a first and a second compound, the first and second compounds each includes a group III element combined with a group V element in the periodic table, the method includes the steps of introducing in the deposition chamber the flux of the group III element for the first compound at substantially the same time while introducing in the deposition chamber a flux of the group V element for the second compound, stopping the flux of the group III element for the first compound after a first predetermined time period, stopping the flux of the group V element for the first compound after a second predetermined time period, and introducing in the deposition chamber a flux of the group III element the group V element for the second compound.09-15-2011

Patent applications by Berinder Brar, Newbury Park, CA US

Berinder P.s. Brar, Newbury Park, CA US

Patent application numberDescriptionPublished
20100240187INTEGRATED SEMICONDUCTOR STRUCTURE INCLUDING A HETEROJUNCTION BIPOLAR TRANSISTOR AND A SCHOTTKY DIODE - An integrated semiconductor structure includes a heterojunction bipolar transistor and a Schottky diode. The structure has a substrate, the heterojunction bipolar transistor overlying and contacting the substrate, wherein the heterojunction bipolar transistor includes a transistor collector layer, and a Schottky diode overlying the substrate and overlying the transistor collector layer. The Schottky diode includes a Schottky diode barrier layer structure that desirably is not of the same material, doping, and thickness as the transistor collector layer.09-23-2010

Patent applications by Berinder P.s. Brar, Newbury Park, CA US

Guni Brar, Gurgaon IN

Patent application numberDescriptionPublished
20110238616SYSTEM AND METHOD FOR IMPROVING OUTCOMES IN ENTERPRISE LEVEL PROCESSES - A method and system for using a data warehouse to improve results of enterprise level processes are provided. The data warehouse typically includes industry-wide empirical data relating to corresponding operational practices, metrics, and outcomes. The method focuses on actual process results by taking a holistic, end-to-end view of the process in conjunction with using the data in the data warehouse to enable effective process improvements.09-29-2011

Tajinder Brar, Kanata, CA US

Patent application numberDescriptionPublished
20110248446Word tree built on consonant nodes - A “word tree” is generated by players of this board game using “consonant” and “vowel” tiles. The distribution of available consonant tiles and the unlimited availability, in principle, of the vowel tiles (“a”, “e”, “i”, “o”, “u”) ensures that almost all words (more than 99%) existing in the English language can be built by a player. A “root word” is placed horizontally, by the first player in the mid-section of the board. The second and subsequent words are built off the consonant tiles already played on the board. It is akin to starting new branches off these “consonant” nodes. The generated tree is bound in a finite rectangular space. The objective of the game is to make “long” words either “new” ones or extensions of those already played. The element of chance in winning this game has been minimized. The game showcases and stimulates knowledge recognition, vocabulary building and articulation.10-13-2011