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Branover

Alex Branover, Brookline, MA US

Patent application numberDescriptionPublished
20080276236DATA PROCESSING DEVICE WITH LOW-POWER CACHE ACCESS MODE - A processor can operate in three different modes. In an active mode, a first voltage is provided to the processor, where the first voltage is sufficient to allow the processor to execute instructions. In a low-power mode, a retention voltage is provided to the processor. The processor consumes less power in the retention mode than in the active mode. In addition, the processor can operate in a third mode, where a voltage is provided to the processor sufficient to allow the processor to process cache messages, such as coherency messages, but not execute other normal operations or perform normal operations at a very low speed relative to their performance in the active mode.11-06-2008
20080288799DYNAMIC PROCESSOR POWER MANAGEMENT DEVICE AND METHOD THEREOF - A processor can operate in different power modes. In an active power mode, the processor executes software. In response to receiving a halt indication from the software, hardware at the processor evaluates bus transactions for the processor. If the bus transactions meet a heuristic, hardware places a processor core in a lower power mode, such as a retention mode. Because the bus transactions are evaluated by hardware, rather than by software, and the software is not required to perform handshakes and other protocols to place the processor in the lower power mode, the processor is able to place the processor core into the lower power mode more quickly, thereby conserving power.11-20-2008
20090235108AUTOMATIC PROCESSOR OVERCLOCKING - Processor overclocking techniques are disclosed. Upon automatically determining that overclocking entry criteria are satisfied, one or more cores are clocked above their standard operation frequencies. The cores may be overclocked until one or more exit criteria are satisfied. At that point, an exit procedure is performed, with the one or more overclocked cores return to their normal operating frequency.09-17-2009

Alexander Branover, Brookline, MA US

Patent application numberDescriptionPublished
20080276026SELECTIVE DEACTIVATION OF PROCESSOR CORES IN MULTIPLE PROCESSOR CORE SYSTEMS - A method includes applying a voltage to a first processor core of a plurality of processor cores to deactivate the first processor core, the voltage less than a retention voltage of the first processor core. The application of the voltage can be in response to a software setting. The software setting can be configured via a user input, a software application, an operating system, or a BIOS setting. Alternately, the application of the voltage can be in response to a permanent hardware setting, such as the state of a fuse associated with the first processor core.11-06-2008

Herman Branover, New York, NY US

Patent application numberDescriptionPublished
20080316782SYSTEM AND METHOD FOR PRODUCTING ANHARMONIC MULTI-PHASE CURRENTS - A system and method for producing anharmonic multi-phase currents wherein the harmonic component of an inverter is filtered and superimposed with a series of control pulses to create a control signal. The control signal is fed back to the inverter, causing the inverter to produce anharmonic multi-phase currents.12-25-2008

Herman D. Branover, New York, NY US

Patent application numberDescriptionPublished
20090021336INDUCTOR FOR THE EXCITATION OF POLYHARMONIC ROTATING MAGNETIC FIELDS - An inductor for the excitation of polyharmonic rotating magnetic fields (RMF) for controlling the crystalline structure of continuous ingots and castings in metallurgy and other foundry applications. The inductor design makes it possible to use standard sources of sinusoidal currents for generating polyharmonic RMF, and significantly increase cos φ of the inductor.01-22-2009