Patent application number | Description | Published |
20100231701 | 3D Stereoscopic Display System for Large Format LED Displays - A three dimensional (3D) stereoscopic display system using large format light emitting diodes (LEDs) for displaying 3D image content. The apparatus comprises a grid of LEDs covered by two sheets of polarizing material, a first sheet of polarizing material for polarizing a first subset of the LEDs to form a first view of the 3D image, and a second sheet of polarizing material for polarizing the second subset of LEDs to form a second view of the 3D image. The sheets may be formed by cutting a plurality of openings substantially aligned with a corresponding subset of LEDs. For improved viewing, the apparatus may further comprise a rear diffuser, disposed between the LED display and the first sheet of polarizing material. Also for improved viewing, the apparatus may further comprise a front diffuser, disposed in front of the second sheet of polarizing material, for reducing glare from external light sources. Also an additional method of the application of individual polarizing buttons directly adhered to the individual LEDs incorporating an assembly key for maintaining the correct orientation of the polarizing material. | 09-16-2010 |
20110063575 | 3D Autostereoscopic Display System With Multiple Sets Of Stereoscopic Views - Multiple sets of view channels originate from multiple projected views modulated through an optic assembly comprising a Fresnel lens, a vertical dispersion lenticular lens, and a diffuser. Compact projection enclosures are formed using image-repeating mirrors to create a three-dimensional autostereoscopic viewing experience in free space without the use of special eyeglasses and without the use of view screens. Multiple sets of images are repeated within a viewing zone that may extend well beyond the confines of the enclosure and may be projected through and beyond a glass window. An observer walking past the window will see one view channel per eye, due in part to the repeated images, and due in part to the vertical dispersion of each projected view. Separate images for each view channel may be created by using two or more cameras spaced apart at a distance interval to match the average horizontal distance between the eyes of a human observer. Multiple views or multiple sets of view channels may be generated and projected. | 03-17-2011 |
20110080639 | METHOD AND APPARATUS FOR DISPLAYING 3-DIMENSIONAL IMAGES INCORPORATING ANGULAR CORRECTION - A technique for encoding a three dimensional image formatted according to a three dimensional format is disclosed. The technique employs a surface or surfaces for encoding a three dimensional image to create a left view image and a right view image. The surface or surfaces may include an arrangement of encoding stripes, black ink stripes, and transparent stripes. The stripes may be arranged in a vertical, horizontal, or checkerboard pattern. The black ink stripes may be further arranged in a manner that corrects an angular viewing error. The encoded right view and left view images are decoded by a left lens and a right lens, respectively, of a pair of polarized 3D viewing glasses worn by a viewer. | 04-07-2011 |
Patent application number | Description | Published |
20080288234 | METHOD, SYSTEM AND PROGRAM PRODUCT SUPPORTING USER TRACING IN A SIMULATOR - According to a method of specifying a trace array for simulation of a digital design, one or more entities within a simulation model are specified with one or more statements in one or more hardware description language (HDL) files. In addition, a trace array for storing data generated through simulation of the simulation model is specified in one or more statements in the one or more HDL files. The HDL files may subsequently be processed to create a simulation model containing at least one design entity and a trace array within the design entity for storing trace data regarding specified signals of interest. | 11-20-2008 |
20090210632 | MICROPROCESSOR AND METHOD FOR DEFERRED STORE DATA FORWARDING FOR STORE BACKGROUND DATA IN A SYSTEM WITH NO MEMORY MODEL RESTRICTIONS - A pipelined processor includes circuitry adapted for store forwarding, including: for each store request, and while a write to one of a cache and a memory is pending; obtaining the most recent value for at least one block of data; merging store data from the store request with the block of data thus updating the block of data and forming a new most recent value and an updated complete block of data; and buffering the updated block of data into a store data queue; for each additional store request, where the additional store request requires at least one updated block of data: determining if store forwarding is appropriate for the additional store request on a block-by-block basis; if store forwarding is appropriate, selecting an appropriate block of data from the store data queue on a block-by-block basis; and forwarding the selected block of data to the additional store request. | 08-20-2009 |
20090210679 | PROCESSOR AND METHOD FOR STORE DATA FORWARDING IN A SYSTEM WITH NO MEMORY MODEL RESTRICTIONS - A pipelined microprocessor includes circuitry for store forwarding by performing: for each store request, and while a write to one of a cache and a memory is pending; obtaining the most recent value for at least one complete block of data; merging store data from the store request with the complete block of data thus updating the block of data and forming a new most recent value and an updated complete block of data; and buffering the updated complete block of data into a store data queue; for each load request, where the load request may require at least one updated completed block of data: determining if store forwarding is appropriate for the load request on a block-by-block basis; if store forwarding is appropriate, selecting an appropriate block of data from the store data queue on a block-by-block basis; and forwarding the selected block of data to the load request. | 08-20-2009 |
20140108743 | STORE DATA FORWARDING WITH NO MEMORY MODEL RESTRICTIONS - Embodiments relate to loading data in a pipelined microprocessor. An aspect includes issuing a load request that comprises a load address requiring at least one block of data the same size as a largest contiguous granularity of data returned from a cache. Another aspect includes determining that the load address matches at least one block address. Another aspect includes, based on determining that there is an address match, reading a data block from a buffer register and sending the data to satisfy the load request; comparing a unique set id of the data block to the set id of the matching address after sending the data block; based on determining that there is a set id match, continuing the load request, or, based on determining that there is not a set id match, setting a store-forwarding state of the matching address to no store-forwarding and rejecting the load request. | 04-17-2014 |