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Bradl

Joachim Bradl, Schriessheim DE

Patent application numberDescriptionPublished
20090257111Tunable Optical Array Device Comprising Liquid Cells - A tunable optical component includes comprises a plurality of individual tunable liquid cells regularly arranged and integrated to at least one cell structure forming an array on the supporting substrate. A single liquid cell comprises several integrated cell walls, the cell walls projecting away from the supporting substrate and having a closed base area and an open cell surface at the cell wall edges. The liquid cell is filled with at least two liquids or fluids to provide at least one tunable interface area for varying the optical characteristic of the liquid cell.10-15-2009

Stephan Bradl, Regensburg DE

Patent application numberDescriptionPublished
20080265383Workpiece with Semiconductor Chips, Semiconductor Device and Method for Producing a Workpiece with Semiconductor Chips - A workpiece has at least two semiconductor chips, each semiconductor chip having a first main surface, which is at least partially exposed, and a second main surface. The workpiece also comprises an electrically conducting layer, arranged on the at least two semiconductor chips, the electrically conducting layer being arranged at least on regions of the second main surface, and a molding compound, arranged on the electrically conducting layer. In the molding compound a contact via is arranged.10-30-2008
20080265421Structure for Electrostatic Discharge in Embedded Wafer Level Packages - A workpiece has at least two semiconductor chips, each semiconductor chip having a first main surface, which is at least partially exposed, and a second main surface. The workpiece also comprises an electrically conducting layer, arranged on the at least two semiconductor chips, the electrically conducting layer being arranged at least on regions of the second main surface, and a molding compound, arranged on the electrically conducting layer.10-30-2008
20090045511INTEGRATED CIRCUIT INCLUDING PARYLENE MATERIAL LAYER - An integrated circuit includes a substrate including a contact pad, a redistribution line coupled to the contact pad, and a dielectric material layer between the substrate and the redistribution line. The integrated circuit includes a solder ball coupled to the redistribution line and a parylene material layer sealing the dielectric material layer and the redistribution line.02-19-2009
20090093127Treatment of a Substrate with a Liquid Medium - The invention relates to an arrangement of electronic semiconductor components on a carrier system for treating the semiconductor components with a liquid medium. A semiconductor component is detachably mounted on the carrier system with the active side thereof in such a way that the arrangement comprises a gap at least in the edge region and partially between the semiconductor components and the carrier system. The aim of the invention is to provide a detachable arrangement of electronic semiconductor components on a mechanically stable carrier system for safely handling the semiconductor components during the production process, wherein the capillarity of the gap between the semiconductor components and the carrier system is reduced in a controlled manner, thus preventing the damaging effect of a liquid medium seeping into the gap. To this end, the surface of the carrier system is shaped in such a way that the gap is widened along the entire edge region thereof.04-09-2009
20090108440SEMICONDUCTOR DEVICE - A semiconductor device is disclosed. One embodiment provides an arrangement of a plurality of semiconductor chips arranged side by side in a spaced apart relationship. A first material fills at least partly the spacings between adjacent semiconductor chips. A second material is arranged over the semiconductor chips and the first material. A coefficient of thermal expansion of the first material is selected to adapt the lateral thermal expansion of the arrangement in a plane intersecting the first material and the semiconductor chips to the lateral thermal expansion of the arrangement in a plane intersecting the second material.04-30-2009
20110147471METHOD FOR PRODUCING A SEMICONDUCTOR WAFER WITH REAR SIDE IDENTIFICATION - A semiconductor wafer with rear side identification and to a method for producing the same is disclosed. In one embodiment, the rear side identification has a multiplicity of information regarding the monocrystalline and surface and also rear side constitution. A multiplicity of semiconductor device positions arranged in rows and columns are provided on the top side of the semiconductor wafer, an information chip being arranged at an exposed semiconductor device position, the information chip having at least the information of the rear side identification.06-23-2011

Patent applications by Stephan Bradl, Regensburg DE

Stephan Bradl, Kofering DE

Patent application numberDescriptionPublished
20110115096ELECTRODEPOSITING A METAL IN INTEGRATED CIRCUIT APPLICATIONS - A method is described in which a contact hole to an interconnect in an insulating layer is fabricated. A barrier layer is subsequently applied. Afterward, a photoresist layer is applied, irradiated and developed. With the aid of a galvanic method, a copper contact is then produced in the contact hole. Either the barrier layer or an additional boundary electrode layer serves as a boundary electrode in the galvanic process. Critical metal contaminations are minimized in production.05-19-2011

Stephen Bradl, Regensburg DE

Patent application numberDescriptionPublished
20110232074METHOD FOR MACHINING A WORKPIECE ON A WORKPIECE SUPPORT - A workpiece machining method includes attaching a workpiece to a workpiece support with the aid of joining means. The workpiece and the workpiece support are joined to one another by an annular joining means. The composite produced is machined. The machined workpiece is separated from the workpiece support.09-29-2011