Patent application number | Description | Published |
20160037099 | IMAGE SENSORS WITH NOISE REDUCTION - In various embodiments, image sensors and methods of operating the image sensors are disclosed. In an example embodiment, a pixel circuit having a first electrode is coupled to a reset transistor and to a first region of an optically sensitive layer, and a second electrode is coupled to a pixel sense node and to a second region of an optically sensitive layer. The electrical path from the first electrode, through the optically sensitive layer, and into the second electrode functions as a variable resistor. Other devices and methods of operating the devices are disclosed. | 02-04-2016 |
20160037114 | SCALING DOWN PIXEL SIZES IN IMAGE SENSORS - In various embodiments, methods and related apparatuses for scaling down pixel sizes in quantum film-based image sensors are disclosed. In one embodiment, an image sensor circuit is disclosed that includes circuit includes an optically sensitive layer, a first pixel having a first electrode coupled to a first region of optically sensitive layer, a second pixel having a second electrode coupled to a second region of optically sensitive layer, and a readout circuit having at least one transistor that is shared among the first pixel and the second pixel. In a first time interval, the transistor is used in a readout of a signal related to illumination of the first pixel over an integration period. During a second time interval, the transistor is used in a readout of a signal related to illumination of the second pixel over an integration pixel. The signals thusly read constitute a time-domain multiplexed (TDM) signal. | 02-04-2016 |
Patent application number | Description | Published |
20090100200 | Channel-less multithreaded DMA controller - A channel-less system and method are provided for multithreaded communications with a direct memory access (DMA) controller. The method accepts a plurality of DMA command messages directed to a fixed port address. The DMA command messages are arranged in a first-in first-out (FIFO) queue, in the order in which they are received. The DMA command messages are supplied to a DMA controller from the FIFO queue, and in response to the DMA command message, data transfer operation are managed by the DMA controller. Following the completion of each data transfer operation, a transfer complete message indicating completion is sent. In one aspect, DMA command messages are arranged in a plurality of parallel FIFO queues, and CD sets are stored in a plurality of context memories, where each context memory is associated with a corresponding FIFO queue. | 04-16-2009 |
20100095039 | INTERRUPT ACKNOWLEDGMENT IN A DATA PROCESSING SYSTEM - A data processing system has an interrupt controller which provides an interrupt request along with a corresponding interrupt identifier and a corresponding interrupt vector to a processor. If the processor accepts the interrupt, the processor returns the same interrupt identifier value by way of interrupt identifier, along with interrupt acknowledge, to the interrupt controller. An interrupt taken/not taken indicator may also be provided. The communications interface used to coordinate interrupt processing between the interrupt controller and the processor may be asynchronous. | 04-15-2010 |
20100125677 | Cache Stashing Processor Control Messages - A system and method have been provided for pushing cacheable control messages to a processor. The method accepts a first control message, identified as cacheable and addressed to a processor, from a peripheral device. The first control message is allocated into a cache that is associated with the processor, but not associated with the peripheral device. In response to a read-prompt the processor reads the first control message directly from the cache. The read-prompt can be a hardware interrupt generated by the peripheral device referencing the first control message. For example, the peripheral may determine that the first control message has been allocated into the cache and generate a hardware interrupt associated with the first control message. Then, the processor reads the first control message in response to the hardware interrupt read-prompt. Alternately, the read-prompt can be the processor polling the cache for pending control messages. | 05-20-2010 |
20100235598 | Using Domains for Physical Address Management in a Multiprocessor System - A multi-processor computer system is provided for managing physical memory domains. The system includes at least one processor having an address interface for sending a memory access message, which includes an address in physical memory and a domain identification (ID). The system also includes a physical memory portioned into a plurality of domains, where each domain includes a plurality of physical addresses. A domain mapping unit (DMU) has an interface to accept the memory access message from the processor. The DMU uses the domain ID to access a permission list, cross-reference the domain ID to a domain including addresses in physical memory, and grant the processor access to the address in response to the address being located in the domain. | 09-16-2010 |
20110022871 | System-On-Chip Queue Status Power Management - A system and method are provided for using queue status to manage power in a system-on-chip (SoC). Messages to be processed are accepted in an SoC with a plurality of selectively enabled processors, and queued. The message traffic can be from an external source via an input/output (IO) interface, or intra-SoC messages between processors. The number of queued messages is monitored and, in response to the number of queued messages exceeding a subscription threshold, one or more processors are enabled. Then, the queued messages are distributed to the enabled processors. Enabling a processor is defined by an action such as supplying power to an unpowered processor, increasing the power supply voltage levels to a processor, increasing the operating frequency of a processor, or a combination of the above-mentioned actions. Likewise, processors can be disabled in response to the number of queued messages falling below the subscription threshold. | 01-27-2011 |
20110145492 | POLYMORPHOUS SIGNAL INTERFACE BETWEEN PROCESSING UNITS - A single interconnect is provided between a first processor and a second processor, such that the first processor may access a common memory through the second processor while the second processor can be mostly powered off. The first processor accesses the memory through a memory controller using a standard dynamic random access memory (DRAM) bus protocol. Instead of the memory controller directly connecting to the memory, the access path is through the second processor to the memory. Additionally, a bidirectional communication protocol bus is mapped to the existing DRAM bus signals. When both the first processor and the second processor are active, the bus protocol between the processors switches from the DRAM protocol to the bidirectional communication protocol. This enables the necessary chip-to-chip transaction semantics without requiring the additional cost burden of a dedicated interface for the bidirectional communication protocol. | 06-16-2011 |
20150317269 | SWITCHING A COMPUTER SYSTEM FROM A HIGH PERFORMANCE MODE TO A LOW POWER MODE - A computer system includes a first processor, a second processor, and a common memory connected to the second processor. The computer system is switched from a high performance mode, in which at least a portion of the first processor and at least a portion of components on the second processor are active, to a low power mode, in which at least a portion of the first processor is active and the components on the second processor are inactive. All central processing unit (CPU) cores on the second processor are quiesced. Traffic from the second processor to the common memory is quiesced. Paths used by the first processor to access the common memory are switched from a first path across the second processor to a second path across the second processor. | 11-05-2015 |
Patent application number | Description | Published |
20130135610 | DEVICE AND METHODS FOR PERFORMING SIZE EXCLUSION CHROMATOGRAPHY - The present invention is directed to a device and a method for performing size exclusion chromatography. Embodiments of the present invention feature devices and methods for size exclusion chromatography at normal high performance liquid chromatography or ultra performance liquid chromatography pressures and above using small particles. | 05-30-2013 |
20130195949 | Antimicrobial Layer For Chromatographic Containers - A chromatographic container ( | 08-01-2013 |
20150129474 | TECHNIQUES FOR THERMALLY INSULATING A LIQUID CHROMATOGRAPHIC COLUMN - An apparatus for performing liquid chromatography includes a chromatography column, and an insulating member surrounding the chromatography column wherein the insulating member is formed from a vacuum chamber surrounding the chromatography column. Another apparatus for performing liquid chromatography includes a chromatography column, and an insulating member surrounding the chromatography column, wherein the insulating member includes aerogel. Also described is a method of insulating a chromatography column comprising forming a jacket surrounding the chromatography column, and creating a vacuum chamber in an area between the jacket and the chromatography column. | 05-14-2015 |
20150157959 | TECHNIQUES FOR ACCELERATING THERMAL EQUILIBRIUM IN A CHROMATOGRAPHIC COLUMN - Techniques are described for accelerating thermal equilibrium in a chromatographic column. An apparatus comprises a chromatography column, and a plurality of temperature control units in thermal contact with the chromatography column. A method of performing liquid chromatography comprises setting an inlet of a chromatography column to a first temperature using a first temperature control unit in thermal contact with said inlet, setting an outlet of the chromatography column to a second temperature using a second temperature control unit in thermal contact with the outlet, wherein the first temperature is less than the second temperature; and injecting a sample into a liquid stream that flows through the chromatography column after the inlet is set at the first temperature and the outlet is at the second temperature. | 06-11-2015 |
Patent application number | Description | Published |
20080305555 | Methods, Compositions and Devices For Performing Ionization Desorption on Silicon Derivatives - A device for the presentation of samples for MALDI or DIOS ion source, comprising a semiconductor wafer body having at least one first surface and at least one second surface, the first surface being chemically modified to repel said aqueous sample toward said second surface. | 12-11-2008 |
20100168457 | MONOLITHIC ELECTROKINETIC PUMP FABRICATION - High-pressure electrokinetic (“EK”) pumps comprising a hybrid monolith provide a high surface charge density and a continuous stable skeleton morphology with micrometer- sized through-pores. The hybrid monolith of the subject invention has superior mechanical strength and better stability in comparison to prior art monoliths with equivalent mechanical stability. The surface charge of the hybrid monolith can be modified and/or made stable by the use of different chemical reagents. The chemical reagents and resulting modification to the monolith serves to expand the usefulness of the hybrid monolith to a variety of pumping applications including chip-based systems and other applications where the ability to pump an acidic solution is required. | 07-01-2010 |
20110259089 | Devices Having An Inert Surface And Methods Of Making Same - The present invention features devices and methods of making such devices for performing liquid chromatography having at least one wetted surface having a composition of a polysilazane. | 10-27-2011 |
20120125843 | METHODS AND MATERIALS FOR PERFORMING HYDROPHOBIC INTERACTION CHROMATOGRAPHY - A method for performing hydrophobic interaction chromatography includes providing at least one wall defining a chamber having an inlet and an exit, and a stationary phase disposed within the chamber. The stationary phase comprises particles or monolith having a hydrophobic surface and a hydrophilic ligand. The method also includes loading a sample onto the stationary phase in the chamber and flowing the sample over the stationary phase. The sample is separated into one or more compositions by hydrophobic interaction between the stationary phase and the one or more compositions. | 05-24-2012 |
20130068043 | APPARATUS AND METHODS FOR PREPARATION AND ANALYSIS OF DRIED SAMPLES OF A BIOLOGICAL FLUID - Described is a device for collecting a fluid sample, such as a biological fluid sample. The device includes a planar collection substrate having an absorbent material. The planar collection substrate includes an impermeable region and a sample collection region. The impermeable region is impermeable to the fluid sample and is embedded in the planar collection substrate in a spatial pattern. The sample collection region is in an area excluded from the spatial pattern and has a shape and a size defined by the spatial pattern. The sample collection region is configured to receive a known volume of the fluid sample. In an alternative form, the device includes a sample collection element disposed in an impermeable planar holder and, in another alternative form, the device includes an absorbent material disposed inside an impermeable tube wall. | 03-21-2013 |
20140220278 | Porous Material And Devices For Performing Separations, Filtrations, And Catalysis And EK Pumps, And Mthods Of Making And Using The Same - Embodiments of the present invention are directed to a porous monolith polymeric composition having utility in catalysis, chromatography, filtration, and electro-kinetic pumps, devices incorporating such composition and methods or making and using such monoliths. The monoliths are characterized by a substantially homogeneous skeletal core with little shrinkage, few voids and few channels. | 08-07-2014 |
Patent application number | Description | Published |
20130211390 | SYSTEM AND METHOD FOR SCANNING A PULSED LASER BEAM - Systems and methods of photoaltering a region of a material using a pulsed laser beam. The method includes scanning the pulsed laser beam in a first portion of the region with a first pattern, scanning the pulsed laser beam in a second portion of the region with a second pattern, and separating a flap of the material at the region. The system includes a laser, a controller selecting at least first and second patterns, and a scanner operable in response to the controller. The first pattern has a first maximum acceleration associated with the second portion, and the second pattern has a second maximum acceleration associated with the second portion. The second maximum acceleration is less than the first maximum acceleration. The scanner scans the pulsed laser beam from the laser in the first portion with the first pattern and in the second portion with the second pattern. | 08-15-2013 |
20150190282 | METHOD FOR SCANNING A PULSED LASER BEAM - Methods of photoaltering a region of a material using a pulsed laser beam. The method includes scanning the pulsed laser beam in a first portion of the region with a first pattern, scanning the pulsed laser beam in a second portion of the region with a second pattern, and separating a flap of the material at the region. The system includes a laser, a controller selecting at least first and second patterns, and a scanner operable in response to the controller. The first pattern has a first maximum acceleration associated with the second portion, and the second pattern has a second maximum acceleration associated with the second portion. The second maximum acceleration is less than the first maximum acceleration. The scanner scans the pulsed laser beam from the laser in the first portion with the first pattern and in the second portion with the second pattern. | 07-09-2015 |
20150190283 | METHOD FOR SCANNING A PULSED LASER BEAM - Systems and methods of photoaltering a region of a material using a pulsed laser beam. The method includes scanning the pulsed laser beam in a first portion of the region with a first pattern, scanning the pulsed laser beam in a second portion of the region with a second pattern, and separating a flap of the material at the region. The system includes a laser, a controller selecting at least first and second patterns, and a scanner operable in response to the controller. The first pattern has a first maximum acceleration associated with the second portion, and the second pattern has a second maximum acceleration associated with the second portion. The second maximum acceleration is less than the first maximum acceleration. The scanner scans the pulsed laser beam from the laser in the first portion with the first pattern and in the second portion with the second pattern. | 07-09-2015 |
Patent application number | Description | Published |
20080253294 | Data link fault tolerance - A method is provided for automatically generating code to define and control a system of connected hardware elements. The method comprises: accepting a system configuration macro with sub-macros for system elements, subsystem elements, and connections there between; accepting a plurality of tables with a plurality of system element behaviors, a plurality of subsystem element behaviors, and a plurality of connection options; defining the system of connected elements in response to selecting sub-macros; defining the physical links between the system elements and the behavior of the system and subsystem elements in response to populating the selected sub-macro parameters; expanding the selected sub-macros; generating executable code; and, accessing the tables in response to parameters in the executable code. Advantageously, the form and function of the system can be defined with programming, or writing application specific code. | 10-16-2008 |
20080256455 | Method for Defining the Physical Configuration of a Communication System - A method is provided for automatically generating code to define and control a system of connected hardware elements. The method comprises: accepting a system configuration macro with sub-macros for system elements, subsystem elements, and connections there between; accepting a plurality of tables with a plurality of system element behaviors, a plurality of subsystem element behaviors, and a plurality of connection options; defining the system of connected elements in response to selecting sub-macros; defining the physical links between the system elements and the behavior of the system and subsystem elements in response to populating the selected sub-macro parameters; expanding the selected sub-macros; generating executable code; and, accessing the tables in response to parameters in the executable code. Advantageously, the form and function of the system can be defined with programming, or writing application specific code. | 10-16-2008 |