| Patent application number | Description | Published |
|---|
| 20090080280 | Electronic memory device - An electronic memory device includes a bank of memories provided with a cache, a sequencer for providing physical access to said bank of memories, a physical interface for receiving high level memory access requests, a request manager between the physical interface and the sequencer, said request manager includes an input queue for storing the high level memory access requests and an arbitration function which takes account of the data of the cache and the data of the input queue to designate a request which is to be executed, thus allowing the memory bank, the sequencer and the request manager to be provided on a single chip, the physical interface providing the connection of the chip with the outside. | 03-26-2009 |
| 20100122004 | MESSAGE SWITCHING SYSTEM - The message switching system comprises at least two inputs and at least one output, first arbitration means dedicated to said output, and management means designed to determine a relative order OR(i,j) of one input relative to the other, for any pair of separate inputs belonging to the system and having sent requests for the assignment of said output, and designed to assign said output. Said management means comprise storage means designed to store said relative orders OR(i,j), initialization means designed to initialize said relative orders OR(i,j) such that only one of said inputs takes priority on initialization, and updating means designed to update all of said relative orders when a new request arrives at said first arbitration means, or when said output is assigned to one of said inputs. | 05-13-2010 |
| 20100180163 | METHOD AND DEVICE FOR SWITCHING BETWEEN AGENTS - In some embodiments, a system for communication between agents in a point-to-point interconnection system includes at least one initiator agent capable of dispatching at least one message destined for at least one determined receiver agent; at least one intermediate agent capable of forwarding at least one message to at least one determined receiver agent; at least one receiver agent capable of receiving at least one message originating from an initiator agent via at least one intermediate agent; and means of error detection and means of erroneous message marking. In some embodiments, a receiver agent includes means for formulating an error message and means for sending the error message to the initiator agent so as to warn the said initiator agent of the presence of an error. | 07-15-2010 |
| 20100296400 | Method and Device for Managing Priority During the Transmission of a Message - Method of managing priority during the transmission of a message, in an interconnections network comprising at least one transmission agent which comprises at least one input and at least one output, each input comprising a means of storage organized as a queue of messages. A message priority is assigned during the creation of the message, and a queue priority equal to the maximum of the priorities of the messages of the queue is assigned to at least one queue of messages of an input. A link priority is assigned to a link linking an output of a first transmission agent to an input of a second transmission agent, equal to the maximum of the priorities of the queues of messages of the inputs of said first agent comprising a first message destined for that output of said first agent which is coupled to said link, and the priority of the link is transmitted to that input of said second agent which is coupled to the link. | 11-25-2010 |
| 20110085550 | Zero-latency network on chip (NoC) - Packet format configurability is extended for packets transported on physical links of an Intellectual Property (IP) core interconnect by using at least two independent parameters: one parameter governing data-width and one parameter governing latency penalty. The at least two independent parameters allow creation of transport protocol packets without additional latency insertion, which is useful for low-latency applications. The at least two independent parameters also allow creation of narrow packets with multi-cycle additional latency, which is useful for latency tolerant, area sensitive applications. | 04-14-2011 |
