Patent application number | Description | Published |
20090267154 | MOS COMPRISING SUBSTRATE POTENTIAL ELEVATING CIRCUITRY FOR ESD PROTECTION - An integrated circuit ( | 10-29-2009 |
20100169064 | SYSTEM, AN APPARATUS AND A METHOD FOR PERFORMING CHIP-LEVEL ELECTROSTATIC DISCHARGE SIMULATIONS - A modeler for components of an IC under ESD conditions, a method of simulating ESD behavior of an IC and an ESD simulation system. In one embodiment, the modeler includes: (1) a circuit analyzer configured to provide identified ESD cells and circuitry of the IC by comparing component information of the IC with predefined ESD protection elements and predefined circuit topologies and (2) a model generator configured to create linearized models of the identified ESD cells and the identified circuitry based on physical attributes associated with the identified ESD cells and the identified circuitry, wherein a combination of the linearized models represent operation of the IC component under ESD conditions. | 07-01-2010 |
20100169845 | METHOD OF OPTIMIZING ESD PROTECTION FOR AN IC, AN ESD PROTECTION OPTIMIZER AND AN ESD PROTECTION OPTIMIZATION SYSTEM - An ESD protection optimizer, a method of optimizing ESD protection for an IC and an ESD protection optimization system is disclosed. In one embodiment, the ESD protection optimizer includes: (1) a circuit analyzer configured to identify ESD cells and circuitry of the IC by comparing component information of the IC with predefined ESD protection elements and predefined circuit topologies and (2) an ESD resistance determiner configured to calculate a resistance value to couple in series with the circuitry, the resistance value based on protection cell physical attributes associated with the identified ESD cells and circuitry physical attributes associated with the identified circuitry. | 07-01-2010 |
20100169854 | ESD PROTECTION VALIDATOR, AN ESD VALIDATION SYSTEM AND A METHOD OF VALIDATING ESD PROTECTION FOR AN IC - Disclosed is an electrostatic discharge (ESD) protection validator, a method of validating ESD protection for an IC and an ESD validation system. In one embodiment, the ESD protection validator includes: (1) a circuit analyzer configured to compare component information of the IC with predefined ESD protection elements to identify ESD cells of the IC and (2) an ESD cell verifier configured to compare physical attributes associated with the identified ESD cells to ESD protection requirements and determine compliance therewith. | 07-01-2010 |
20110063765 | MOS DEVICE WITH SUBSTRATE POTENTIAL ELEVATION FOR ESD PROTECTION - An integrated circuit ( | 03-17-2011 |
20130264640 | DRAIN EXTENDED MOS TRANSISTOR HAVING SELECTIVELY SILICIDED DRAIN - A method of forming a drain extended metal-oxide-semiconductor (MOS) transistor includes forming a gate structure including a gate electrode on a gate dielectric on a semiconductor surface portion of a substrate. The semiconductor surface portion has a first doping type. A source is formed on one side of the gate structure having a second doping type. A drain is formed including a highly doped portion on another side of the gate structure having the second doping type. A masking layer is formed on a first portion of a surface area of the highly doped drain portion. A second portion of the surface area of the highly doped drain portion does not have the masking layer. Selectively siliciding is used to form silicide on the second portion. The masking layer blocks siliciding on the first portion so that the first portion is silicide-free. | 10-10-2013 |
20130285114 | TWIN-WELL LATERAL SILICON CONTROLLED RECTIFIER - A LSCR includes a substrate having a semiconductor surface which is p-doped. A first nwell and a second nwell spaced apart from one another are in the semiconductor surface by a lateral spacing distance. A first n+ diffusion region and a first p+ diffusion region are in the first nwell. A second n+ diffusion region is in the second nwell. A second p+ diffusion is between the first nwell and second nwell which provides a contact to the semiconductor surface. Dielectric isolation is between the first n+ diffusion region and first p+ diffusion region, along a periphery between the first nwell and the semiconductor surface, and along a periphery between the second nwell and the semiconductor surface. A resistor provides coupling between the second n+ diffusion region and second p+ diffusion. | 10-31-2013 |
20130285196 | ESD PROTECTION CIRCUIT PROVIDING MULTIPLE PROTECTION LEVELS - An electrostatic discharge (ESD) protection circuit includes a substrate having a semiconductor surface. A plurality of stacked ESD protection cells are in the semiconductor surface each having a surrounding isolation structure, wherein the ESD protection cells are connected in series by an interconnect and include a first ESD protection cell in series with at least a second ESD protection cell. A plurality of protection pins include a first protection pin across the first ESD protection cell but not across the second ESD protection cell to provide a first voltage rating and a second protection pin across both the first and second ESD protection cell to provide a second voltage rating which is higher than the first voltage rating. | 10-31-2013 |
20130320396 | MUTUAL BALLASTING MULTI-FINGER BIDIRECTIONAL ESD DEVICE - An integrated circuit includes a bidirectional ESD device which has a plurality of parallel switch legs. Each switch leg includes a first current switch and a second current switch in a back-to-back configuration. A first current supply node of each first current switch is coupled to a first terminal of the ESD device. A second current supply node of each second current switch is coupled to a second terminal of the ESD device. A first current collection node of each first current switch is coupled to a second current collection node of the corresponding second current switch. The first current collection nodes in each first current switch is not coupled to any other first current collection node, and similarly, the second current collection node in each instance second current switch is not coupled to any other second current collection node. | 12-05-2013 |
20140184237 | PACKAGED DEVICE FOR DETECTING FACTORY ESD EVENTS - An ESD monitor device may take the form of an integrated circuit with a plurality of monitor components available at each I/O site of the ESD monitor device. Each monitor component has a physical structure which provides scalable ESD robustness. The monitor components are connected in parallel to an ESD bus. An integrated circuit may be formed by processing an ESD monitor device through one or more process steps of an integrated circuit manufacturing line, and subsequently measuring the ESD monitor device. Parameters of a process step of the manufacturing line may be adjusted to reduce ESD events at the process step, based on measurement results from the ESD monitor device. The integrated circuit may subsequently be processed through the adjusted process step. | 07-03-2014 |
Patent application number | Description | Published |
20100037998 | Aluminum alloy products having improved property combinations and method for artificially aging same - Aluminum alloy products about 4 inches thick or less that possesses the ability to achieve, when solution heat treated, quenched, and artificially aged, and in parts made from the products, an improved combination of strength, fracture toughness and corrosion resistance, the alloy consisting essentially of: about 6.8 to about 8.5 wt. % Zn, about 1.5 to about 2.00 wt. % Mg, about 1.75 to about 2.3 wt. % Cu; about 0.05 to about 0.3 wt. % Zr, less than about 0.1 wt. % Mn, less than about 0.05 wt. % Cr, the balance Al, incidental elements and impurities and a method for making same. The instantly disclosed alloys are useful in making structural members for commercial airplanes including, but not limited to, upper wing skins and stringers, spar caps, spar webs and ribs of either built-up or integral construction. | 02-18-2010 |
20120225271 | 2XXX SERIES ALUMINUM LITHIUM ALLOYS - Thick wrought 2xxx aluminum lithium alloy products are disclosed. The wrought aluminum alloy products have a thickness of at least 12.7 mm and contain from 3.00 to 3.80 wt. % Cu, from 0.05 to 0.35 wt. % Mg, from 0.975 to 1.385 wt. % Li, wherein −0.3*Mg−0.15Cu+1.65≦Li≦−0.3*Mg−0.15Cu+1.85, from 0.05 to 0.50 wt. % of at least one grain structure control element, wherein the grain structure control element is selected from the group consisting of Zr, Sc, Cr, V, Hf, other rare earth elements, and combinations thereof, up to 1.0 wt. % Zn, up to 1.0 wt. % Mn, up to 0.12 wt. % Si, up to 0.15 wt. % Fe, up to 0.15 wt. % Ti, up to 0.10 wt. % of any other element, with the total of these other elements not exceeding 0.35 wt. %, the balance being aluminum. | 09-06-2012 |
20130302206 | 2XXX SERIES ALUMINUM LITHIUM ALLOYS - New 2xxx aluminum lithium alloys are disclosed. The aluminum alloys include 3.5-4.4 wt. % Cu, 0.45-0.75 wt. % Mg, 0.45-0.75 wt. % Zn, 0.65-1.15 wt. % Li, 0.1-1.0 wt. % Ag, 0.05-0.50 wt. % of at least one grain structure control element, up to 1.0 wt. % Mn, up to 0.15 wt. % Ti, up to 0.12 wt. % Si, up to 0.15 wt. % Fe, up to 0.10 wt. % of any other element, with the total of these other elements not exceeding 0.35 wt. %, the balance being aluminum. | 11-14-2013 |
20140050936 | 2XXX SERIES ALUMINUM LITHIUM ALLOYS - Wrought 2xxx aluminum lithium alloy products having a thickness of from 0.040 inch to 0.500 inch are disclosed. The wrought aluminum alloy products contain from 3.00 to 3.80 wt. % Cu, from 0.05 to 0.35 wt. % Mg, from 0.975 to 1.385 wt. % Li, wherein −0.3*Mg−0.15Cu+1.65≦Li≦−0.3*Mg−0.15Cu+1.85, from 0.05 to 0.50 wt. % of at least one grain structure control element, wherein the grain structure control element is selected from the group consisting of Zr, Sc, Cr, V, Hf, other rare earth elements, and combinations thereof, up to 1.0 wt. % Zn, up to 1.0 wt. % Mn, up to 0.12 wt. % Si, up to 0.15 wt. % Fe, up to 0.15 wt. % Ti, up to 0.10 wt. % of any other element, with the total of these other elements not exceeding 0.35 wt. %, the balance being aluminum. | 02-20-2014 |
Patent application number | Description | Published |
20080223492 | Edge-On Stress-Relief of Aluminum Plates - In accordance with the present invention, there are provided methods for the manufacture of aluminum alloy plates having reduced levels of residual stress as well as plates and products employing such plates. Processes of the present invention involve providing a solution heat-treated and quenched aluminum alloy plate with a thickness of at least 5 inches, and stress relieving the plate by performing at least one compressing step at a total rate of 0.5 to 5% permanent set along the longest or second longest edge of the plate. In the method, the dimension of the plate where the compression step is performed is along the longest or second longest edge of the plate, which is preferably no less than twice and no more than eight times the thickness of the plate. In further accordance with the present invention, there are provided stress-relieved alloys and plates that are provided with superior W | 09-18-2008 |
20080236708 | Process For Manufacturing Structural Components By Machining Plates - The present invention includes a process for manufacturing metal sheets or plates and a machined metal part as well as machined products, structural components and their uses in various applications. Manufacture of a metal sheet or plate by a process of the present invention comprises casting of a rolling ingot, optionally followed by homogenisation, one or more hot or cold rolling operations, optionally separated by one or more re-heating operations, to obtain a sheet, or plate and optionally one or more sheet or plate cutting or finishing operations. The sheet is pre-machined on one or both sides so as to obtain a pre-machined stock, and subjected to solution heat treatment, quenching treatment, and optionally, one or more of the following steps: controlled stretching, aging treatment, and/or cutting. | 10-02-2008 |