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Bordawekar
Rajesh Bordawekar, Yorktown Heights, NY US
| Patent application number | Description | Published |
|---|---|---|
| 20090031175 | SYSTEM AND METHOD FOR ANALYZING STREAMS AND COUNTING STREAM ITEMS ON MULTI-CORE PROCESSORS - Systems and methods for parallel stream item counting are disclosed. A data stream is partitioned into portions and the portions are assigned to a plurality of processing cores. A sequential kernel is executed at each processing core to compute a local count for items in an assigned portion of the data stream for that processing core. The counts are aggregated for all the processing cores to determine a final count for the items in the data stream. A frequency-aware counting method (FCM) for data streams includes dynamically capturing relative frequency phases of items from a data stream and placing the items in a sketch structure using a plurality of hash functions where a number of hash functions is based on the frequency phase of the item. A zero-frequency table is provided to reduce errors due to absent items. | 01-29-2009 |
| 20110125730 | Optimizing Queries to Hierarchically Structured Data - Techniques are disclosed for optimizing queries to hierarchically structured data. For example, a method for processing a query directed to data having a hierarchical structure with a plurality of data nodes comprises the following steps. One or more structural attributes describing the hierarchical structure of the data are identified. The query is partitioned into two or more query partitions using at least one of the one or more identified structural attributes. A parallel execution plan is determined for the query by splitting into components one or more of: the query into at least two of the query partitions; and the hierarchical structure of the data. The split components are executed in parallel on different computer processes according to the parallel execution plan. | 05-26-2011 |
Rajesh R. Bordawekar, Yorktown Heights, NY US
| Patent application number | Description | Published |
|---|---|---|
| 20090144528 | METHOD FOR RUNNING NATIVE CODE ACROSS SINGLE OR MULTI-CORE HYBRID PROCESSOR ACHITECTURE - Provided is a method that enables an interpretive engine to execute in a non-homogeneous, multiple processor architecture. Am interpretive engine is modified to identify code native to a target processor that is executing an ISA different than the ISA of the processor executing the interpretive engine. An intermediate function is called to correlate the native code with a processor type and a target processor is identified. A context is created for the native code and the context is either transmitted to the target processor or stored in a memory location such that the target processor may retrieve the context. Once the context is transmitted, the target processor executes the task. Results are either transmitted to the originating processor or placed in memory such that the originating processor can access the result and the originating processor is signaled of the completion of the task. | 06-04-2009 |
| 20110078133 | Searching Multi-Dimensional Data - Techniques for searching multi-dimensional data are provided. The techniques include providing a parallelization framework for a search algorithm, wherein the search algorithm exposes one or more architecture-sensitive tunable optimization parameters, and using the one or more architecture-sensitive tunable optimization parameters to tune the search algorithm to search multi-dimensional data in any underlying architecture. | 03-31-2011 |
| 20110078226 | Sparse Matrix-Vector Multiplication on Graphics Processor Units - Techniques for optimizing sparse matrix-vector multiplication (SpMV) on a graphics processing unit (GPU) are provided. The techniques include receiving a sparse matrix-vector multiplication, analyzing the sparse matrix-vector multiplication to identify one or more optimizations, wherein analyzing the sparse matrix-vector multiplication to identify one or more optimizations comprises analyzing a non-zero pattern for one or more optimizations and determining whether the sparse matrix-vector multiplication is to be reused across computation, optimizing the sparse matrix-vector multiplication, wherein optimizing the sparse matrix-vector multiplication comprises optimizing global memory access, optimizing shared memory access and exploiting reuse and parallelism, and outputting an optimized sparse matrix-vector multiplication. | 03-31-2011 |
Rajesh Ramkrishna Bordawekar, Yorktown Heights, NY US
| Patent application number | Description | Published |
|---|---|---|
| 20100076940 | METHOD FOR PROVIDING MAXIMAL CONCURRENCY IN A TREE STRUCTURE - Techniques for providing maximal concurrency while ensuring no deadlock in a tree structure are provided. The techniques include accessing a minimum number of one or more nodes to perform an operation. | 03-25-2010 |
Rajesh Ramkrishna Bordawekar, Hawthorne, NY US
| Patent application number | Description | Published |
|---|---|---|
| 20110202745 | METHOD AND APPARATUS FOR COMPUTING MASSIVE SPATIO-TEMPORAL CORRELATIONS USING A HYBRID CPU-GPU APPROACH - A CPU may select a variable from a variable set as a dependent variable. The variable set may be part of the data structure that includes a plurality of vector values, a vector value associated with a variable set of n number of variables, and each variable of the variable set having a variable value. The number of dependent variable steps for the dependent variable may be determined. The number of the vector values in a dependent variable step is determined as being number of independent variables. A function is mapped to a plurality of thread processors, and each thread processor is assigned for the function to be performed on each one of the independent variables for each of the dependent variable steps. | 08-18-2011 |