Patent application number | Description | Published |
20100213536 | Nonvolatile Memory Device and Method of Forming the Same - A nonvolatile memory device includes a device isolation pattern, a charge trap layer, and a plurality of word lines. The device isolation pattern defines an active region in a semiconductor substrate and extends in a first direction. The charge trap layer covers the active region and the device isolation pattern. The word lines on the charge trap layer cross the active region and extend in a second direction. The charge trap layer disposed in a first region where the word line and the active region cross each other has a different nitrogen content ratio from the charge trap layer disposed in a second region surrounding the first region. | 08-26-2010 |
20100227479 | Semiconductor device and associated methods of manufacture - Provided are a semiconductor device and a method of fabricating the same. The method includes forming a metal nitride layer and a metal oxide layer on a semiconductor substrate to be in contact with each other, and annealing the substrate including the metal nitride layer and the metal oxide layer to form a metal oxynitride layer. | 09-09-2010 |
20110215392 | Semiconductor Devices and Methods of Manufacturing the Same - Provided are a semiconductor device and a method of manufacturing the semiconductor device. The semiconductor device includes a charge storage pattern formed on a substrate; a dielectric pattern formed on the charge storage pattern; a first conductive pattern including silicon doped with a first impurity of a first concentration, the first conductive pattern being disposed on the dielectric pattern; and a second conductive pattern including metal silicide doped with a second impurity of a second concentration, the second conductive pattern being disposed on the first conductive pattern. The first concentration may be higher than the second concentration. | 09-08-2011 |
20130260554 | Semiconductor Devices and Methods of Manufacturing the Same - Provided are a semiconductor device and a method of manufacturing the semiconductor device. The semiconductor device includes a charge storage pattern formed on a substrate; a dielectric pattern formed on the charge storage pattern; a first conductive pattern including silicon doped with a first impurity of a first concentration, the first conductive pattern being disposed on the dielectric pattern; and a second conductive pattern including metal silicide doped with a second impurity of a second concentration, the second conductive pattern being disposed on the first conductive pattern. The first concentration may be higher than the second concentration. | 10-03-2013 |
20150132909 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE USING PLASMA DOPING PROCESS AND SEMICONDUCTOR DEVICE MANUFACTURED BY THE METHOD - A method of manufacturing a semiconductor device includes forming a preliminary fin-type active pattern extending in a first direction, forming a device isolation pattern covering a lower portion of the preliminary fin-type active pattern, forming a gate structure extending in a second direction and crossing over the preliminary fin-type active pattern, forming a fin-type active pattern having a first region and a second region, forming a preliminary impurity-doped pattern on the second region by using a selective epitaxial-growth process, and forming an impurity-doped pattern by injecting impurities using a plasma doping process, wherein the upper surface of the first region is at a first level and the upper surface of the second region is at a second level lower than the first level. | 05-14-2015 |
20150145018 | Semiconductor Devices - Provided are a semiconductor device and a method of manufacturing the semiconductor device. The semiconductor device includes a charge storage pattern formed on a substrate; a dielectric pattern formed on the charge storage pattern; a first conductive pattern including silicon doped with a first impurity of a first concentration, the first conductive pattern being disposed on the dielectric pattern; and a second conductive pattern including metal silicide doped with a second impurity of a second concentration, the second conductive pattern being disposed on the first conductive pattern. The first concentration may be higher than the second concentration. | 05-28-2015 |
20150147861 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE USING SURFACE TREATMENT AND SEMICONDUCTOR DEVICE MANUFACTURED BY THE METHOD - A method of manufacturing a semiconductor device includes forming a first plurality of recessed regions in a substrate, the substrate having a protruded active region between the first plurality of recessed regions and the protruded active region having an upper surface and a sidewall, forming a device isolation film in the first plurality of recessed regions, the device isolation film exposing the upper surface and an upper portion of the sidewall of the protruded active region, and performing a first plasma treatment on the exposed surface of the protruded active region, wherein the plasma treatment is performed using a plasma gas containing at least one of an inert gas and a hydrogen gas in a temperature of less than or equal to about 700. | 05-28-2015 |
20150206956 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing a semiconductor device includes forming an active pattern protruding from a semiconductor substrate, forming a dummy gate pattern crossing over the active pattern, forming gate spacers on opposite first and second sidewalls of the dummy gate pattern, removing the dummy gate pattern to form a gate region exposing an upper surface and sidewalls of the active pattern between the gate spacers, recessing the upper surface of the active pattern exposed by the gate region to form a channel recess region, forming a channel pattern in the channel recess region by a selective epitaxial growth (SEG) process, and sequentially forming a gate dielectric layer and a gate electrode covering an upper surface and sidewalls of the channel pattern in the gate region. The channel pattern has a lattice constant different from that of the semiconductor substrate. | 07-23-2015 |