Patent application number | Description | Published |
20110145559 | SYSTEM AND METHOD FOR CONTROLLING CENTRAL PROCESSING UNIT POWER WITH GUARANTEED STEADY STATE DEADLINES - A method of dynamically controlling a central processing unit is disclosed. The method may include determining when a CPU enters a steady state, calculating an optimal frequency for the CPU when the CPU enters a steady state, guaranteeing a steady state CPU utilization, and guaranteeing a steady state CPU utilization deadline. | 06-16-2011 |
20110145605 | SYSTEM AND METHOD FOR DYNAMICALLY CONTROLLING A PLURALITY OF CORES IN A MULTICORE CENTRAL PROCESSING UNIT BASED ON TEMPERATURE - A method of controlling power within a multicore central processing unit (CPU) is disclosed. The method may include monitoring a die temperature, determining a degree of parallelism within a workload of the CPU, and powering one or more cores of the CPU up or down based on the degree of parallelism, the die temperature, or a combination thereof. | 06-16-2011 |
20110145615 | SYSTEM AND METHOD FOR CONTROLLING CENTRAL PROCESSING UNIT POWER BASED ON INFERRED WORKLOAD PARALLELISM - A method of dynamically controlling power within a multicore CPU is disclosed and may include receiving a degree of parallelism in a workload of a zeroth core and determining whether the degree of parallelism in the workload of the zeroth core is equal to a first wake condition. Further, the method may include determining a time duration for which the first wake condition is met when the degree of parallelism in the workload of the zeroth core is equal to the first wake condition and determining whether the time duration is equal to a first confirm wake condition. The method may also include invoking an operating system to power up a first core when the time duration is equal to the first confirm wake condition. | 06-16-2011 |
20110145616 | SYSTEM AND METHOD FOR CONTROLLING CENTRAL PROCESSING UNIT POWER IN A VIRTUALIZED SYSTEM - A method of dynamically controlling power within a multicore central processing unit is disclosed and includes executing a plurality of virtual cores, virtually executing one or more tasks, one or more threads, or a combination thereof at the virtual cores, and physically executing one or more tasks, one or more threads, or a combination thereof at a zeroth physical core. The method may further include receiving a degree of parallelism in a workload of a plurality of virtual cores and determining whether the degree of parallelism in the workload of the virtual cores is equal to a first wake condition. | 06-16-2011 |
20110145617 | SYSTEM AND METHOD FOR CONTROLLING CENTRAL PROCESSING UNIT POWER WITH GUARANTEED TRANSIENT DEADLINES - A method of controlling power at a central processing unit is disclosed. The method may include moving to a higher CPU frequency after a transient performance deadline has expired, entering an idle state, and resetting the transient performance deadline based on an effective transient budget. | 06-16-2011 |
20110145624 | SYSTEM AND METHOD FOR ASYNCHRONOUSLY AND INDEPENDENTLY CONTROLLING CORE CLOCKS IN A MULTICORE CENTRAL PROCESSING UNIT - A method of controlling core clocks in a multicore central processing unit is disclosed and may include executing a zeroth dynamic clock and voltage scaling (DCVS) algorithm on a zeroth core and executing a first DCVS algorithm on a first core. The zeroth DCVS algorithm may operable to independently control a zeroth clock frequency associated with the zeroth core and the first DCVS algorithm may be operable to independently control a first clock frequency associated with the first core. | 06-16-2011 |
20110145824 | SYSTEM AND METHOD FOR CONTROLLING CENTRAL PROCESSING UNIT POWER WITH REDUCED FREQUENCY OSCILLATIONS - A method of dynamically controlling power within a central processing unit is disclosed and may include entering an idle state, reviewing a previous busy cycle immediately prior to the idle state, and based on the previous busy cycle determining a CPU frequency for a next busy cycle. | 06-16-2011 |
20110202709 | OPTIMIZING STORAGE OF COMMON PATTERNS IN FLASH MEMORY - One embodiment of the present invention provides a method of operation within a flash memory system. During operation, the system receives write data and a corresponding logical address. The system then determines whether the write data matches a predetermined data pattern. If the write data does match the predetermined data pattern, instead of writing the data, the system records an indication that the predetermined data pattern corresponds to the logical address. | 08-18-2011 |
20110257966 | SYSTEM AND METHOD OF PROVIDING VOICE UPDATES - A method of providing voice updates is disclosed and may include receiving a voice update. The method may also include scheduling a voice update window. The voice update window may be a predetermined time window in which a voice update is broadcast. | 10-20-2011 |
20110286267 | Pattern-Sensitive Coding of Data for Storage in Multi-Level Memory Cells - A method of operating a memory device includes receiving first and second sets of bits to be stored in multi-level cells in the device. A multi-level encoding is selected from among a plurality of multi-level encodings for storing the first and second sets of bits in the multi-level cells. Each multi-level encoding includes at least four encoding levels for a respective multi-level cell. Respective multi-level encodings have respective costs associated with programming the first and second sets of bits into the multi-level cells in accordance with the respective multi-level encodings. The multi-level encoding is selected based on the respective costs of the respective encodings. The first and second sets of bits are encoded in accordance with the selected multi-level encoding to produce encoded data for storage in the device such that a respective multi-level cell stores respective bits from both the first and second sets of bits. | 11-24-2011 |
20110289510 | ATOMIC-OPERATION COALESCING TECHNIQUE IN MULTI-CHIP SYSTEMS - A cache-coherence protocol distributes atomic operations among multiple processors (or processor cores) that share a memory space. When an atomic operation that includes an instruction to modify data stored in the shared memory space is directed to a first processor that does not have control over the address(es) associated with the data, the first processor sends a request, including the instruction to modify the data, to a second processor. Then, the second processor, which already has control of the address(es), modifies the data. Moreover, the first processor can immediately proceed to another instruction rather than waiting for the address(es) to become available. | 11-24-2011 |
20120042155 | METHODS AND APPARATUS FOR PROACTIVE BRANCH TARGET ADDRESS CACHE MANAGEMENT - A multiple stage branch prediction system includes a branch target address cache (BTAC) and a branch predictor circuit. The BTAC is configured to store a BTAC entry. The branch predictor circuit is configured to store state information. The branch predictor circuit utilizes the state information to predict the direction of a branch instruction and to manage the BTAC entry based on modified state information prior to resolution of the branch instruction. | 02-16-2012 |
20120102249 | Arbitrating Bus Transactions on a Communications Bus Based on Bus Device Health Information and Related Power Management - Devices, systems, methods, and computer-readable mediums for arbitrating bus transactions on a communications bus based on health information are disclosed. Health information of master devices can be used to adjust priorities of bus transactions from master devices to meet quality of service requirements of the master devices. In one embodiment, a bus interconnect is provided and configured to communicate bus transactions from any of a plurality of master devices to slave device(s) coupled the bus interconnect. The bus interconnect is further configured to map health information for each of the plurality of master devices into virtual priority space. The bus interconnect is further configured to translate the virtual priority space into a physical priority level for each of the plurality of master devices. The bus interconnect is further configured to arbitrate bus transactions for the plurality of master devices based on physical priority level for the plurality of master devices. | 04-26-2012 |
20120117317 | ATOMIC MEMORY DEVICE - In an integrated-circuit memory device having a memory core, a first data value is retrieved from an address-specified location within the memory core in response to a memory access command. The first data value is output from the memory device in response to the memory access command, and a second data value is stored in the address-specified location within the memory core in response to the memory access command. | 05-10-2012 |
20120179303 | METHOD AND SYSTEM FOR MANAGING THERMAL POLICIES OF A PORTABLE COMPUTING DEVICE - A method and system for managing one or more thermal policies of a portable computing device (PCD) includes monitoring temperature of the portable computing device with internal thermal sensors and external thermal sensors. If a change in temperature has been detected by at least one thermal sensor, then a thermal policy manager may increase a frequency in which temperature readings are detected by the thermal sensors. The thermal policy manager may also determine if a current temperature of the portable computing device as detected by one or more of the thermal sensors falls within one or more predetermined thermal states. Each thermal state may be assigned a unique set of thermal mitigation techniques. Each set of thermal mitigation techniques may be different from one another. The sets of thermal mitigation techniques may differ according to quantity of techniques and impacts on performance of the PCD. | 07-12-2012 |
20120179416 | METHOD AND SYSTEM FOR MANAGING THERMAL POLICIES OF A PORTABLE COMPUTING DEVICE - A method and system for managing one or more thermal policies of a portable computing device (PCD) includes monitoring temperature of the portable computing device with internal thermal sensors and external thermal sensors. If a change in temperature has been detected by at least one thermal sensor, then a thermal policy manager may increase a frequency in which temperature readings are detected by the thermal sensors. The thermal policy manager may also determine if a current temperature of the portable computing device as detected by one or more of the thermal sensors falls within one or more predetermined thermal states. Each thermal state may be assigned a unique set of thermal mitigation techniques. Each set of thermal mitigation techniques may be different from one another. The sets of thermal mitigation techniques may differ according to quantity of techniques and impacts on performance of the PCD. | 07-12-2012 |
20120226888 | Memory Management Unit With Pre-Filling Capability - Systems and method for memory management units (MMUs) configured to automatically pre-fill a translation lookaside buffer (TLB) with address translation entries expected to be used in the future, thereby reducing TLB miss rate and improving performance. The TLB may be pre-filled with translation entries, wherein addresses corresponding to the pre-fill may be selected based on predictions. Predictions may be derived from external devices, or based on stride values, wherein the stride values may be a predetermined constant or dynamically altered based on access patterns. Pre-filling the TLB may effectively remove latency involved in determining address translations for TLB misses from the critical path. | 09-06-2012 |
20120260179 | METHOD AND APPARATUS FOR OPTIMIZED EXECUTION USING RESOURCE UTILIZATION MAPS - Systems and methods enable displaying a graphical representation of system resource usage in a resource utilization map to inform users about system resource utilization by applications and processes running on a computing device. Users may provide inputs to enable the system to adjust resource allocations based on user preferences. This may enable users to improve the overall operational performance of the device consistent with their current personal preferences by identifying applications or processes of most or least interest so the device processor to prioritize system resources accordingly. Some aspects transmit resource allocation data based on such user input to a central server to enable community based resource allocation schemes. Community based resource allocation schemes may be transmitted to computing devices for use as default or preliminary resource allocations for particular applications, websites or device operating states. | 10-11-2012 |
20120260258 | METHOD AND SYSTEM FOR DYNAMICALLY CONTROLLING POWER TO MULTIPLE CORES IN A MULTICORE PROCESSOR OF A PORTABLE COMPUTING DEVICE - A method and system for dynamically determining the degree of workload parallelism and to automatically adjust the number of cores (and/or processors) supporting a workload in a portable computing device are described. The method and system includes a parallelism monitor module that monitors the activity of an operating system scheduler and one or more work queues of a multicore processor and/or a plurality of central processing units (“CPUs”). The parallelism monitor may calculate a percentage of parallel work based on a current mode of operation of the multicore processor or a plurality of processors. This percentage of parallel work is then passed to a multiprocessor decision algorithm module. The multiprocessor decision algorithm module determines if the current mode of operation for the multicore processor (or plurality of processors) should be changed based on the calculated percentage of parallel work. | 10-11-2012 |
20130029695 | System and Method of Providing Voice Updates - Various embodiments of methods and systems for providing informational updates, such as directional updates, to a user of a computing device are disclosed. Certain embodiments may include receiving a voice update while the user is using other functionality of the computing device, such as a telecommunication function. Embodiments may also include scheduling an update window within which the update may be delivered. The update window may be a predetermined time window in which a voice update is broadcast, for example. Embodiments may also include alerting the user to a pending update. | 01-31-2013 |
20130074085 | SYSTEM AND METHOD FOR CONTROLLING CENTRAL PROCESSING UNIT POWER WITH GUARANTEED TRANSIENT DEADLINES - Methods, systems and devices that include a dynamic clock and voltage scaling (DCVS) solution configured to compute and enforce performance guarantees to ensure that a processor does not remain in a busy state (e.g., due to transient workloads) for more than a predetermined amount of time above that which is required for that processor to complete its pre-computed steady state workload. The DCVS may adjust the frequency and/or voltage of a processor based on a variable delay to ensure that the processing core only falls behind its steady state workload by, at most, a predefined maximum amount of work, irrespective of the operating frequency or voltage of the processor. | 03-21-2013 |
20130078977 | Method and System For Selecting a Thermally Optimal Uplink For A Portable Computing Device - A method and system for selecting a thermally optimal airlink for a portable computing device includes monitoring a temperature of the portable computing device as well as determining if the portable computing device has reached a threshold temperature range. Next, an estimated volume of data to be sent over one or more airlinks may be calculated in addition to determining an estimated duration for the data using one or more airlinks. A quality of service needed for the data in connection with the one or more airlinks may be determined. With this estimated data, one or more available airlinks for the data to be transmitted may be compared. After this comparison, one or more thermally optimal airlinks may be selected based on the estimated volume, estimated data rate, and estimated duration. Determining if the portable computing device is proximate to an operator may be used when considering airlinks. | 03-28-2013 |
20130097415 | Central Processing Unit Monitoring and Management Based On A busy-Idle Histogram - The aspects enable a computing device or microprocessor to adjust the operations of a processor in view of a current processor workload based on a histogram-like data structure. A histogram-like data structure characterizing one of processor busy and/or idle durations or busy/idle ratios is generated at runtime and used to model the processor workload. The processor workload is used to predict future processing requirements and to adjust the processor's operations such that they are commensurate with the processing and workload requirements. The histogram-like data structure may alternatively be used to estimate a current quality of service (QoS) of a communication link so that link management actions may be taken. | 04-18-2013 |
20130132972 | THERMALLY DRIVEN WORKLOAD SCHEDULING IN A HETEROGENEOUS MULTI-PROCESSOR SYSTEM ON A CHIP - Various embodiments of methods and systems for thermally aware scheduling of workloads in a portable computing device that contains a heterogeneous, multi-processor system on a chip (“SoC”) are disclosed. Because individual processing components in a heterogeneous, multi-processor SoC may exhibit different processing efficiencies at a given temperature, and because more than one of the processing components may be capable of processing a given block of code, thermally aware workload scheduling techniques that compare performance curves of the individual processing components at their measured operating temperatures can be leveraged to optimize quality of service (“QoS”) by allocating workloads in real time, or near real time, to the processing components best positioned to efficiently process the block of code. | 05-23-2013 |
20130151879 | SYSTEM AND METHOD FOR CONTROLLING CENTRAL PROCESSING UNIT POWER WITH GUARANTEED TRANSIENT DEADLINES - Methods, systems and devices that include a dynamic clock and voltage scaling (DCVS) solution configured to compute and enforce performance guarantees for a group of processors to ensure that the processors does not remain in a busy state (e.g., due to transient workloads) for a combined period that is more than a predetermined amount of time above that which is required for one of the processors to complete its pre-computed steady state workload. The DCVS may adjust the frequency and/or voltage of one or more of the processors based on a variable delay to ensure that the multiprocessor system only falls behind its steady state workload by, at most, a predefined maximum amount of work, irrespective of the operating frequency or voltage of the processors. | 06-13-2013 |
20140040552 | MULTI-CORE COMPUTE CACHE COHERENCY WITH A RELEASE CONSISTENCY MEMORY ORDERING MODEL - A method includes storing, with a first programmable processor, shared variable data to cache lines of a first cache of the first processor. The method further includes executing, with the first programmable processor, a store-with-release operation, executing, with a second programmable processor, a load-with-acquire operation, and loading, with the second programmable processor, the value of the shared variable data from a cache of the second programmable processor. | 02-06-2014 |
20140181542 | System and Method For Dynamically Controlling A Plurality Of Cores In A Multicore Central Processing Unit Based On Tempature - A method of controlling power within a multicore central processing unit (CPU) is disclosed. The method may include monitoring a die temperature, determining a degree of parallelism within a workload of the CPU, and powering one or more cores of the CPU up or down based on the degree of parallelism, the die temperature, or a combination thereof. | 06-26-2014 |
20140189710 | THERMALLY DRIVEN WORKLOAD SCHEDULING IN A HETEROGENEOUS MULTI-PROCESSOR SYSTEM ON A CHIP - Various embodiments of methods and systems for thermally aware scheduling of workloads in a portable computing device that contains a heterogeneous, multi-processor system on a chip (“SoC”) are disclosed. Because individual processing components in a heterogeneous, multi-processor SoC may exhibit different processing efficiencies at a given temperature, and because more than one of the processing components may be capable of processing a given block of code, thermally aware workload scheduling techniques that compare performance curves of the individual processing components at their measured operating temperatures can be leveraged to optimize quality of service (“QoS”) by allocating workloads in real time, or near real time, to the processing components best positioned to efficiently process the block of code. | 07-03-2014 |