Patent application number | Description | Published |
20080218755 | SEMICONDUCTOR UV ABSORPTIVE PHOTOMETRIC CELLS - Biomolecules in solid or liquid form are targeted with a UV beam of about 260 nm that is attenuated by absorption in the biomolecules. The attenuated light passes through a UV transmissive window and partly discharges an underlying floating gate EPROM device. The incremental partial discharge of the floating gate device alters the threshold voltage of the device and is read by an analog output amplifier. Variation in threshold voltage of the device is measured with respect to the extent of optical absorption by the biomolecules resulting in photometric data. A biomolecule target array can be fabricated as an X-Y array in a chip or wafer over an array of correspondingly spaced EPROM devices with control devices forming cells with each cell separately readable. | 09-11-2008 |
20090109720 | Memory Structure - The subject matter of this specification can be embodied in, among other things, a method for manufacturing and a structure of a byte-addressable electrically erasable programmable read-only memory (EEPROM). In a first aspect, a byte-addressable EEPROM integrated circuit includes isolation means, in each of a plurality of memory bytes, for electrically isolating the EEPROM byte select transistor from an EEPROM memory bit disposed closest to the byte select transistor. In one example, the isolation means precludes the need to use a wide STI oxide for isolation, and thereby avoids the process variation of active area of memory bits. | 04-30-2009 |
20090114951 | MEMORY DEVICE - A memory device can be implemented including word lines connected to an array of memory transistors. Each memory transistor is also connected to bit lines and a select transistor. The select transistors each have their sources connected to a conductive source line, by a shunt and the gate of each select transistor is connected to a select line. | 05-07-2009 |
20090141554 | MEMORY DEVICE HAVING SMALL ARRAY AREA - Memory arrays can be implemented including word lines connected to memory transistors and corresponding select transistors. Each memory transistor is also connected to an array select transistor. Each select transistor is also connected to a bit line. The memory transistors are arranged such that they define bytes of data. A well line is connected to each portion of the semiconductor substrate that defines an array of bytes. | 06-04-2009 |
20090194804 | NON-VOLATILE MEMORY CELL - Disclosed herein are non-volatile cells and methods of manufacturing the same. The nonvolatile memory cells include a high voltage device, a low voltage device, and a memory cell formed on a semiconductor substrate. The high voltage device, low voltage device, and memory cell are all self-aligned by using the gates associated with each of the devices as a mask during formation of the respective sources and drains. | 08-06-2009 |
20090273015 | NON-VOLATILE MEMORY CELL - This document discloses non-volatile memory cells and methods of manufacturing the same. The non-volatile memory cells are self-aligned and have a reduced tunnel window area that is within an active region of a substrate. The tunnel window area can be reduced using mask openings without optical proximity correction that define tunnels having one or more curvatures. | 11-05-2009 |
20090279361 | Addressable Memory Array - This document discloses non-volatile memory cells and methods of manufacturing the same. The memory arrays are byte, word, and/or page addressable without using a byte select transistor. The byte select transistor is eliminated by using the well, memory transistor control gates, and select transistor gates to selectively program a byte, word, or page. | 11-12-2009 |
20100019306 | Semiconductor Fabrication - This document discloses devices fabricated on a semiconductor substrate and methods of fabricating the same. The devices can be memory cells having a tunnel window that is defined by dry-etching oxide to expose the semiconductor substrate and growing a tunnel oxide layer on the exposed semiconductor substrate. The semiconductor substrate can be decontaminated and/or repaired by exposing the semiconductor substrate to an optical irradiated energy source having a predefined energy that is sufficient to break molecular bonds of the contaminants and exposing the semiconductor substrate to a temperature that is sufficient to recrystallize the crystal lattice of the substrate. | 01-28-2010 |
20100022072 | Semiconductor Fabrication - This document discloses devices fabricated on a semiconductor substrate and methods of fabricating the same. The devices can be memory cells having a tunnel window that is defined by dry-etching oxide to expose the semiconductor substrate and growing a tunnel oxide layer on the exposed semiconductor substrate. The semiconductor substrate can be decontaminated and/or repaired by exposing the semiconductor substrate to an optical irradiated energy source having a predefined energy that is sufficient to break molecular bonds of the contaminants and exposing the semiconductor substrate to a temperature that is sufficient to recrystallize the crystal lattice of the substrate. | 01-28-2010 |
20100059508 | SEMICONDUCTOR PROCESSING - This document discloses semiconductor processing systems, methods, and devices. The systems, methods and devices activate dopants in a processing chamber having a temperature that is less than, for example, 300 degrees. A microwave energy source provides a microwave transmission to a waveguide system that uniformly distributes the microwave transmission. The waveguide system can include a rectangular waveguide coupled to a cylindrical waveguide. The rectangular waveguide guides the microwave transmission in a second propagation direction to a cylindrical waveguide. The cylindrical waveguide uniformly distributes the electromagnetic transmission and guides the electromagnetic transmission in a third propagation direction to a processing chamber. A semiconductor wafer can be exposed to the microwave transmission and the temperature of the chamber to activate dopants in the semiconductor wafer. | 03-11-2010 |