Patent application number | Description | Published |
20090116585 | ANALOG FRONT-END HAVING BUILT-IN EQUALIZATION AND APPLICATIONS THEREOF - An analog front-end having built-in equalization includes a control module and a tunable gain stage. The control module is operably coupled to provide a frequency response setting based on a channel response of a channel providing high-speed serial data to the analog front-end. The tunable gain stage includes a frequency dependent load and an amplifier input section. The frequency dependent load is adjusted based on the frequency response setting. The amplifier input section is operably coupled to the frequency dependent load and receives the high-speed serial data. In conjunction with the frequency dependent load, the amplifier input section amplifies and equalizes the high-speed serial data to produce an amplified and equalized serial data. | 05-07-2009 |
20130154698 | DELAY-LOCKED LOOP WITH PHASE ADJUSTMENT - A delay-lock loop includes two feedback loops for controlling delay elements in the delay-lock loop. The first feedback loop includes a feedback circuit for generating a feedback signal indicating a delay adjustment based on a phase difference between an input clock signal to the delay-locked loop and an output clock signal generated by the delay-locked loop. The second feedback loop includes a power regulator that generates a regulated signal by regulating a power supply using the feedback signal as a reference. The delay-lock loop further includes a variable delay circuit including a resistor-capacitor network. The variable delay circuit controls a capacitance in the resistor-capacitor network based on the feedback signal and controls a resistance of the resistor-capacitor network based on the regulated signal. In this way, variable delay circuit generates the output clock signal by delaying the input clock signal based on both the feedback signal and the regulated signal. | 06-20-2013 |
20130342241 | Pseudo-Supply Hybrid Driver - A hybrid output driver includes a voltage mode main driver having an adjustable differential output voltage swing, and a current mode emphasis driver. Differential output voltage swing is adjusted by controlling the resistance of a first adjustable resistor coupled to a first voltage supply terminal, and the resistance of a second adjustable resistor coupled to a second voltage supply terminal. Resistances of the first and second adjustable resistors are adjusted by modifying a number of resistors connected in parallel. A calibration process measures the actual resistance of a similar resistor, and uses this resistance measurement to determine the number of resistors to be connected in parallel to provide the desired resistance. The current mode emphasis driver sources/sinks currents to/from differential output terminals of the hybrid output driver in response to an emphasis signal. These currents are selected in view of the selected differential output voltage swing and selected emphasis level. | 12-26-2013 |
20140210531 | DELAY-LOCKED LOOP WITH INDEPENDENT PHASE ADJUSTMENT OF DELAYED CLOCK OUTPUT PAIRS - A delay-lock loop includes two feedback loops for controlling delay elements in the delay-lock loop. The first feedback loop includes a feedback circuit for generating a feedback signal indicating a delay adjustment based on a phase difference between an input clock signal to the delay-locked loop and an output clock signal generated by the delay-locked loop. The second feedback loop includes a power regulator that generates a regulated signal by regulating a power supply using the feedback signal as a reference. The delay-lock loop further includes a variable delay circuit including a resistor-capacitor network. The variable delay circuit controls a capacitance in the resistor-capacitor network based on the feedback signal and controls a resistance of the resistor-capacitor network based on the regulated signal. In this way, variable delay circuit generates the output clock signal by delaying the input clock signal based on both the feedback signal and the regulated signal. | 07-31-2014 |
20140218083 | DELAY-LOCKED LOOP WITH DUAL LOOP FILTERS FOR FAST RESPONSE AND WIDE FREQUENCY AND DELAY RANGE - A delay-lock loop includes two feedback loops for controlling delay elements in the delay-lock loop. The first feedback loop includes a feedback circuit for generating a feedback signal indicating a delay adjustment based on a phase difference between an input clock signal to the delay-locked loop and an output clock signal generated by the delay-locked loop. The second feedback loop includes a power regulator that generates a regulated signal by regulating a power supply using the feedback signal as a reference. The delay-lock loop further includes a variable delay circuit including a resistor-capacitor network. The variable delay circuit controls a capacitance in the resistor-capacitor network based on the feedback signal and controls a resistance of the resistor-capacitor network based on the regulated signal. In this way, variable delay circuit generates the output clock signal by delaying the input clock signal based on both the feedback signal and the regulated signal. | 08-07-2014 |
20150244381 | DELAY-LOCKED LOOP WITH DUAL LOOP FILTERS FOR FAST RESPONSE AND WIDE FREQUENCY AND DELAY RANGE - A delay-lock loop includes two feedback loops for controlling delay elements in the delay-lock loop. The first feedback loop includes a feedback circuit for generating a feedback signal indicating a delay adjustment based on a phase difference between an input clock signal to the delay-locked loop and an output clock signal generated by the delay-locked loop. The second feedback loop includes a power regulator that generates a regulated signal by regulating a power supply using the feedback signal as a reference. The delay-lock loop further includes a variable delay circuit including a resistor-capacitor network. The variable delay circuit controls a capacitance in the resistor-capacitor network based on the feedback signal and controls a resistance of the resistor-capacitor network based on the regulated signal. In this way, variable delay circuit generates the output clock signal by delaying the input clock signal based on both the feedback signal and the regulated signal. | 08-27-2015 |
20150263737 | DELAY-LOCKED LOOP WITH INDEPENDENT PHASE ADJUSTMENT OF DELAYED CLOCK OUTPUT PAIRS - A delay-lock loop includes two feedback loops for controlling delay elements in the delay-lock loop. The first feedback loop includes a feedback circuit for generating a feedback signal indicating a delay adjustment based on a phase difference between an input clock signal to the delay-locked loop and an output clock signal generated by the delay-locked loop. The second feedback loop includes a power regulator that generates a regulated signal by regulating a power supply using the feedback signal as a reference. The delay-lock loop further includes a variable delay circuit including a resistor-capacitor network. The variable delay circuit controls a capacitance in the resistor-capacitor network based on the feedback signal and controls a resistance of the resistor-capacitor network based on the regulated signal. In this way, variable delay circuit generates the output clock signal by delaying the input clock signal based on both the feedback signal and the regulated signal. | 09-17-2015 |
Patent application number | Description | Published |
20090282416 | VITAL PRODUCT DATA COLLECTION DURING PRE-STANDBY AND SYSTEM INITIAL PROGRAM LOAD - A system for selectively recollecting vital product data during an initial program load at data processing system power on. In response to receiving an input to power on a data processing system, a resource location code array table is accessed within a set of selected tables for the data processing system based on machine type. The selected set of tables is located in firmware within a service processor. An entry for a resource in the resource location code array table is read to determine whether the entry includes a no recollect tag. Then, in response to determining that the entry for the resource in the resource location code array table does include a no recollect tag, vital product data for the resource is not recollected during the initial program load. | 11-12-2009 |
20120185637 | RECOVERING FAILED WRITES TO VITAL PRODUCT DATA DEVICES - A method for maintaining vital product data (VPD) contained in an EEPROM (Electrically Erasable Programmable Read-Only Memory) on a field replaceable unit (FRU) of a computer system that has a cache. The method includes maintaining a copy of the VPD in the cache, retrieving the copy of the VPD from the cache upon receiving a read request of the VPD, and, upon receiving a write request to write data to the VPD, writing the data to the copy of the VPD, determining whether the VPD in the EEPROM is in synchronization with the copy of the VPD in the cache, and, if the VPD and the copy of the VPD are in synchronization, writing the data to the EEPROM. | 07-19-2012 |
20120185724 | PARITY-BASED VITAL PRODUCT DATA BACKUP - A method for maintaining vital product data (VPD) of each field replaceable unit (FRUs) in a computer system, the computer system including a first FRU and a second FRU operatively coupled with the first FRU. The method includes calculating a parity for the VPD of the second FRU, and upon detecting a failure of the second FRU, regenerating the VPD for the failed second FRU using the parity. | 07-19-2012 |
20130067134 | PSEUDO MULTI-MASTER I2C OPERATION IN A BLADE SERVER CHASSIS - A system and method are directed towards a pseudo multi-master operation on a serial bus. The pseudo multi-master operation allows multiple devices without standard multi-master functionality to operate on the serial bus as masters. In a disclosed example, the serial bus is an Inter-Integrated Circuit (I2C) bus, which is isolated when an adapter card requires access to the I2C bus, such as to update vital product data (VPD) to a memory device, and to cache the updated VPD to a chassis management module. | 03-14-2013 |