Patent application number | Description | Published |
20100213864 | CHANGING POWER INPUT TO A GAS DISCHARGE LAMP - The present disclosure thus provides a technique for providing multi-level operation of ballast circuitry for discharge lamps. In one version, an auxiliary capacitance is switched in and out of circuit by a user controlled switch for lower the frequency of the voltage from the inverter to the transformer resulting in lower power output to the lamps. In another version, the auxiliary capacitance may be switched in and out of circuit by a user operated switch wherein the capacitance is connected to the secondary or output winding of the transformer for selectively reducing power to the lamps for reduced illumination. In other versions, auxiliary inductances are selectively switched in and out of circuit to alter the frequency of the primary voltage to the transformer. In another version, an auxiliary winding is selectively switched in and out of the secondary of the transformer for providing normal and reduced level power to the lamps. In another version, a variable direct current power supply is provided to the coupled inductors of the ballast circuitry for user control of the power supply to the ballast circuitry. | 08-26-2010 |
20100327763 | BALLAST WITH END-OF-LIFE PROTECTION FOR ONE OR MORE LAMPS - Ballasts are presented with improved end-of-life (EOL) detection of lamp DC voltage components and protection circuits to facilitate user maintenance and extend lamp life using selective dimming with preheating when EOL conditions are detected. | 12-30-2010 |
20120002447 | GATE DRIVE CONTROLLER CIRCUIT WITH ANTI-SATURATION CIRCUIT AND POWER UP CIRCUIT THEREFOR - A high side isolated gate drive controller circuit is presented with an on-time limiting circuit to prevent isolation transformer saturation as well as a universal power up circuit adaptable to power the driver with constant voltage for different input voltage levels. | 01-05-2012 |
20120129320 | METHOD OF NISIGE EPITAXIAL GROWTH BY INTRODUCING AL INTERLAYER - The present invention discloses a method of NiSiGe epitaxial growth by introducing Al interlayer, comprising the deposition of an Al thin film on the surface of SiGe layer, subsequent deposition of a Ni layer on Al thin film and then the annealing process for the reaction between Ni layer and SiGe material of SiGe layer to form NiSiGe material. Due to the barrier effect of Al interlayer, NiSiGe layer features a single crystal structure, a flat interface with SiGe substrate and a thickness of up to 0.3 nm, significantly enhancing interface performance. | 05-24-2012 |
20120136687 | System and Method for CAPA Process Automation - The present disclosure involves systems, products, and methods for automatically generating a CAPA plan. One method includes operations for identifying an issue associated with a business system; identifying a set of information associated with the issue including a plurality of evaluation factors defining the issue; identifying a set of weighting values associated with the issue, each weighting values associated with a particular evaluation factor; evaluating the issue based on the plurality of evaluation factors combined with the corresponding weighting value, determining at least one root cause for the issue based on the evaluation results, identifying at least one corrective or preventive action based at least in part on the at least one determined root cause for the issue, and automatically generating the CAPA plan including the at least one determined root cause and the at least one identified corrective or preventive action associated with the issue. | 05-31-2012 |
20120206969 | Memory Array - A memory array used in the field of semiconductor technology includes a plurality of memory cells, bit lines, word lines perpendicular to the bit lines, and first/second control lines. The memory array uses split-gate memory cells, wherein two memory bit cells of a memory cell share one word line, thereby the read, program and erase of the memory cell can be realized by applying different voltages to the word line, two control gates and source/drain regions; the word line sharing structure enables a split-gate flash memory to effectively reduce the chip area and avoid over-erase problems while maintaining electrical isolation performance of the chip unchanged and not increasing the complexity of the process. | 08-16-2012 |
20130029478 | METHOD OF FABRICATING HIGH-MOBILITY DUAL CHANNEL MATERIAL BASED ON SOI SUBSTRATE - The present invention discloses a method of fabricating high-mobility dual channel material based on SOI substrate, wherein compressive strained SiGe is epitaxially grown on a conventional SOI substrate to be used as channel material of PMOSFET; Si is then epitaixally grown on SiGe, and approaches such as ion implantation and annealing are employed to allow relaxation of part of strained SiGe and transfer strain to the Si layer thereon so as to form strained Si material as channel material of NMOSFET. With simple process and easy realization, this method can provide high-mobility channel material for NMOSFET and PMOSFET at the same time, well meeting the requirement of simultaneously enhancing the performance of NMOSFET and PMOSFET devices and therefore providing potential channel material for CMOS process of the next generation. | 01-31-2013 |
20130323798 | METHOD OF USING ALPHA-AMYLASE FROM ASPERGILLUS CLAVATUS FOR SACCHARIFICATION - A fungal α-amylase is provided from | 12-05-2013 |
20140055033 | PROGRAMMED START CIRCUIT FOR BALLAST - A programmed start ballast circuit is presented having a mode control circuit to selectively switch an inverter output load to control operation for cathode preheating, step dimming and/or anti-arcing operation. | 02-27-2014 |
20140160853 | MEMORY ARRAY - A memory array used in the field of semiconductor technology includes a plurality of memory cells, bit lines, word lines perpendicular to the bit lines, and first/second control lines. The memory array uses split-gate memory cells, wherein two memory bit cells of a memory cell share one word line, thereby the read, program and erase of the memory cell can be realized by applying different voltages to the word line, two control gates and source/drain regions; the word line sharing structure enables a split-gate flash memory to effectively reduce the chip area and avoid over-erase problems while maintaining electrical isolation performance of the chip unchanged and not increasing the complexity of the process. | 06-12-2014 |
20140169099 | MEMORY ARRAY - A memory array used in the field of semiconductor technology includes a plurality of memory cells, bit lines, word lines perpendicular to the bit lines, and first/second control lines. The memory array uses split-gate memory cells, wherein two memory bit cells of a memory cell share one word line, thereby the read, program and erase of the memory cell can be realized by applying different voltages to the word line, two control gates and source/drain regions; the word line sharing structure enables a split-gate flash memory to effectively reduce the chip area and avoid over-erase problems while maintaining electrical isolation performance of the chip unchanged and not increasing the complexity of the process. | 06-19-2014 |