Patent application number | Description | Published |
20090253855 | Polycarbonate-Polysiloxane Copolymer Resin Composition with High Impact Strength at Low Temperature and Mechanical Strength and Method for Preparing the Same - Disclosed herein is a polycarbonate-polysiloxane copolymer resin composition comprising: (A) about 100 parts by weight of a thermoplastic polycarbonate resin; and (B) about 0.1 to about 30 parts by weight of an organic siloxane polymer having a primary amine group. The polycarbonate-polysiloxane copolymer resin composition has high impact strength at low temperature and high mechanical strength. | 10-08-2009 |
20100106404 | METHOD FOR MANAGING SCHEDULE USING USER'S LOCATION INFORMATION AND SYSTEM THEREOF - A method for managing a schedule using a user's location information includes: registering a schedule which includes the user's location information; detecting the user's location; and sending a message related to the schedule or the user's location. | 04-29-2010 |
20120225382 | METHOD FOR MANUFACTURING TONER - A method of preparing toner. Due to the use of an inorganic salt of a monovalent metal as a coagulant when toner particles are aggregated, formed toner particles have a narrow particle size distribution, low-temperature fixability, and high image quality. | 09-06-2012 |
20120288793 | METHOD FOR PRODUCING TONER - Disclosed is a method for producing toner. The method for producing toner by emulsion aggregation according to the present invention, comprises adjusting viscosity at a homogenization stage, to thereby obtain toner particles having a dense particle size distribution via a simple process. | 11-15-2012 |
20120301821 | METHOD FOR PRODUCING TONER - Disclosed is a method of producing toner. According to the method, a concentration of a dispersion stabilizer, a concentration of an aggregating agent, and a concentration of a hydrogen ion in a reaction solution of an aggregation process are controlled to produce toner particles having a narrow particle size distribution and excellent fixability, and providing a high quality image. | 11-29-2012 |
20120301822 | METHOD FOR PRODUCING TONER - Disclosed is method of preparing toner. According to the method, a concentration of a surfactant, a concentration of an aggregating agent, and a concentration of a hydrogen ion in a reaction solution of an aggregation process are controlled to produce toner particles having a narrow particle size distribution and excellent fixability, and providing a high quality image. | 11-29-2012 |
20130295503 | METHOD FOR MANUFACTURING TONER - Disclosed is a method for manufacturing toner. The method for manufacturing toner according to the present invention uses specific polyester resin to obtain toner with a wide range of fixing temperatures and superior gloss and density of image. | 11-07-2013 |
20140058665 | METHOD FOR MANAGING SCHEDULE USING USER'S LOCATION INFORMATION AND SYSTEM THEREOF - A method for managing a schedule based on a user's location information by a system for managing a schedule. The method comprises receiving a schedule including at least one of an appointment location, appointment contents an appointment time, and appointment target person's phone number from the user; registering the schedule which includes the user's location information by a schedule registration unit of the system; detecting the user's location by a location detection unit of the system; and sending a message related to the schedule or the user's location by a sending unit of the system. The sending of the message related to the schedule or the user's location by the sending unit of the system sends information of a changed appointment time and place to the appointment target person when the user changes the appointment schedule. | 02-27-2014 |
Patent application number | Description | Published |
20120144342 | METHOD AND APPARATUS FOR DISPLAYING LISTS - A list display method and apparatus are disclosed. The list display method, for a terminal having a display unit, includes detecting a necessity for displaying a list, classifying list items into viewable items and aggregated items, displaying the viewable items in the list view region and displaying information regarding the aggregated items in the list aggregate region. Responsive to inputs aggregate items may be classified as viewable items and corresponding ones of the viewable items are classified as aggregate items. | 06-07-2012 |
20150070272 | APPARATUS, METHOD AND RECORDING MEDIUM FOR CONTROLLING USER INTERFACE USING INPUT IMAGE - A method of controlling a user interface using an input image is provided. The method includes storing operation executing information of each of one or more gesture forms according to each of a plurality of functions, detecting a gesture form from the input image, and identifying the operation executing information mapped on the detected gesture form to execute an operation according to a function which is currently operated. | 03-12-2015 |
20150084129 | DUMMY CELL ARRAY FOR FIN FIELD-EFFECT TRANSISTOR DEVICE AND SEMICONDUCTOR INTEGRATED CIRCUIT INCLUDING THE DUMMY CELL ARRAY - A semiconductor device includes a substrate; a device area of the substrate, the device area including a plurality of device unit cells; and a dummy cell array arranged around the device area. The dummy cell array includes a plurality of dummy unit cells repeatedly arranged in a first direction and a second direction perpendicular to the first direction, each of the dummy cell unit having a structure corresponding to a device unit cell. The device unit cell includes at least a first transistor in the device area. The structure of the dummy unit cell includes an active area and a gate line. For each dummy unit cell, the active area and the gate line extend beyond a cell boundary that defines the dummy unit cell. | 03-26-2015 |
20150091188 | SEMICONDUCTOR DEVICE HAVING DUMMY CELL ARRAY - A semiconductor device is disclosed. The semiconductor device includes a plurality of dummy gate lines parallel to each other in a first direction and extending in a second direction that is orthogonal to the first direction; a plurality of first dummy filling patterns between the plurality of dummy gate lines, the first dummy filling patterns parallel to each other in the first direction, and arranged apart from each other in the second direction; a plurality of first dummy vias on the plurality of first dummy filling patterns; and a plurality of first dummy wiring lines connected to the plurality of first dummy vias, the first dummy vias extending in the second direction, and parallel to each other in the first direction. | 04-02-2015 |
Patent application number | Description | Published |
20130127923 | DISPLAY DEVICE AND DRIVING METHOD THEREOF - A display device and a driving method thereof are disclosed. In one aspect, the display device includes a display unit including a plurality of pixels connected to scan lines, light emission control lines, and data lines, where each pixel is configured to emit light with a driving current corresponding to image data signals transmitted through the data lines based on light emission control signals transmitted through the light emission control lines. Each of the pixels includes subpixels, each configured to display one of a plurality of colors. The device also includes a controller configured to convert external video signals to image data signals, output the converted signals to a data driver, generate light emission driving control signals for controlling the light emission duty ratio of the light emission control signals, and calculate the pixel-on-ratio for each subpixel to reduce the driving current. | 05-23-2013 |
20140118426 | DISPLAY DEVICE, APPARATUS FOR COMPENSATING DEGRADATION AND METHOD THEREOF - A display device includes: a plurality of pixels; a degradation compensator for using a temperature weight value for a reference temperature, a luminance weight value for a reference luminance, and a material weight value for a reference material, for calculating a reference using time when a degradation rate of the pixels is changed to a reference degradation rate of a reference degradation curve, and for generating a control variable according to the reference using time; and a power supply for controlling a voltage difference between a first power source voltage for supplying a driving current to the pixels and a second power source voltage according to the control variable. | 05-01-2014 |
Patent application number | Description | Published |
20080216518 | FOREIGN MATERIALS FILTERING APPARATUS AND WASHING MACHINE HAVING THE SAME - In a foreign materials filtering apparatus and a washing machine having the same, a filter unit is not exposed to inside of a washing tub thus not to directly come in contact with laundry, thereby preventing the filter unit and laundry from being damaged and enhancing the entire appearance. Also, the foreign materials filtering apparatus is modularized to facilitate a detachable mounting, thereby enhancing the user's convenience. Additionally, the amount of washing water passing through the foreign materials filtering apparatus is increased by controlling a flowing direction of washing water. Furthermore, foreign materials of washing water are prevented from being introduced into a gap between a washing water circulating duct and a filter unit, thereby enhancing a washing effect. | 09-11-2008 |
20080216519 | FOREIGN MATERIALS FILTERING APPARATUS AND WASHING MACHINE HAVING THE SAME - In a foreign materials filtering apparatus and a washing machine having the same, a filter cover is installed at a washing water circulating duct disposed inside a washing tub, and a net filter is installed at an inner side of the filter cover. Accordingly, the net filter is prevented from directly contacting laundry, thereby preventing the not filter and the laundry from being damaged. Furthermore, since the net filter is covered by the filter cover, the entire appearance is enhanced. Additionally, when the net filter is mounted at the filter cover, the filter unit becomes modularized to be facilitate a detachable mounting. | 09-11-2008 |
20080216520 | FOREIGN MATERIALS FILTERING APPARATUS AND WASHING MACHINE HAVING THE SAME - Disclosed are a foreign materials filtering apparatus and a washing machine having the same. Since a filter cover unit and a filter unit are integrally modularized with each other, a user can separate or mount the filter unit from/to a washing water circulating duct by separating or mounting the filter cover unit from/to the washing water circulating duct. Accordingly, the foreign materials filtering apparatus can be easily detachably mounted at the washing water circulating duct. | 09-11-2008 |
20080216522 | FOREIGN MATERIALS FILTERING APPARATUS AND WASHING MACHINE HAVING THE SAME - In a foreign materials filtering apparatus and a washing machine having the same, owing to a detachable mounting structure between a handle and a front filter and between a rear filter and the front filter, foreign materials collected in a foreign materials filtering space can be easily cleaned. Accordingly, can be solved the conventional problem that a net filter has to be kept inside out at the time of a cleaning process, resulting in causing a user's hands to become dirty. Also, can be solved the conventional problem that there is a difficulty in removing foreign materials from the net filter due to a fibrous characteristic of the net filter. | 09-11-2008 |
20080216523 | FOREIGN MATERIALS FILTERING APPARATUS - In a foreign materials filtering apparatus for a washing machine, a filter unit is not exposed to inside of a washing tub thus not to directly come in contact with laundry. Accordingly, the filter unit and laundry are prevented from being damaged, and the entire appearance is enhanced. Additionally, the foreign materials filtering apparatus is modularized to facilitate a detachable mounting, thereby enhancing the user's convenience. | 09-11-2008 |
20080217243 | METHOD FOR CLEANING FOREIGN MATERIALS FILTERING APPARATUS - In a method for cleaning the foreign materials filtering, foreign materials collected in a foreign materials filtering space can be easily removed under a filter unit is separated from or is mounted at a filter cover unit. As a result, can be solved the conventional problems that a net filter has to be kept inside out at the time of a cleaning process to cause a user's hands to become dirty, and there is a difficulty in removing foreign materials from the net filter due to a fibrous characteristic of the net filter. Accordingly, a cleaning operation for the foreign materials filtering apparatus can be facilitated. | 09-11-2008 |
Patent application number | Description | Published |
20100230741 | SEMICONDUCTOR DEVICES WITH AN AIR GAP IN TRENCH ISOLATION DIELECTRIC - A tunnel insulating layer and a charge storage layer are sequentially stacked on a substrate. A recess region penetrates the charge storage layer, the tunnel insulating layer and a portion of the substrate. The recess region is defined by a bottom surface and a side surface extending from the bottom surface. A first dielectric pattern includes a bottom portion covering the bottom surface and inner walls extending from the bottom portion and covering a portion of the side surface of the recess region. A second dielectric pattern is in the recess region between the inner walls of the first dielectric pattern, and the second dielectric pattern enclosing an air gap. The air gap that is enclosed by the second dielectric pattern may extend through a major portion of the second dielectric pattern in a direction away from the bottom surface of the recess region. | 09-16-2010 |
20110256708 | Methods of Manufacturing Flash Memory Devices by Selective Removal of Nitrogen Atoms - A method of manufacturing a flash memory device includes: forming a dielectric layer on an active region of a substrate having an isolation region and the active region; forming a floating gate on the dielectric layer; forming an isolation layer in the isolation region; forming a nitride layer including a first nitride layer portion formed on an exposed surface of the floating gate and a second nitride layer portion formed on an exposed surface of the isolation layer; selectively removing nitrogen atoms from the second nitride layer portion of the nitride layer; forming an inter-gate dielectric layer on both the first nitride layer portion and the isolation layer; and forming a control gate on the inter-gate dielectric layer. | 10-20-2011 |
20110306195 | METHOD OF MANUFACTURING VERTICAL SEMICONDUCTOR DEVICES - In a vertical semiconductor device and a method of manufacturing a vertical semiconductor device, sacrificial layers and insulating interlayers are repeatedly and alternately stacked on a substrate. The sacrificial layers include boron (B) and nitrogen (N) and have an etching selectivity with respect to the insulating interlayers. Semiconductor patterns are formed on the substrate through the sacrificial layers and the insulating interlayers. The sacrificial layers and the insulating interlayers are at least partially removed between the semiconductor patterns to form sacrificial layer patterns and insulating interlayer patterns on sidewalls of the semiconductor patterns. The sacrificial layer patterns are removed to form grooves between the insulating interlayer patterns. The grooves expose portions of the sidewalls of the semiconductor patterns. A gate structure is formed in each of the grooves. | 12-15-2011 |
20130059422 | SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME - Semiconductor devices, and methods of fabricating the same, include forming a trench between a plurality of patterns on a substrate to be adjacent to each other, forming a first sacrificial layer in the trench, forming a first porous insulation layer having a plurality of pores on the plurality of patterns and on the first sacrificial layer, and removing the first sacrificial layer through the plurality of pores of the first porous insulation layer to form a first air gap between the plurality of patterns and under the first porous insulation layer. | 03-07-2013 |
20140084384 | SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME - A semiconductor device includes a plurality of gate structures on a substrate, the plurality of gate structures including a gate metal pattern and delimiting air gaps formed therebetween, an insulating layer on the plurality of gate structures, and a porous insulating layer between the plurality of gate structures and the insulating layer, the porous insulating layer configured to cross the plurality of gate structures to delimit the air gaps. | 03-27-2014 |
20150060988 | SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME - Semiconductor devices, and methods of fabricating the same, include forming a trench between a plurality of patterns on a substrate to be adjacent to each other, forming a first sacrificial layer in the trench, forming a first porous insulation layer having a plurality of pores on the plurality of patterns and on the first sacrificial layer, and removing the first sacrificial layer through the plurality of pores of the first porous insulation layer to form a first air gap between the plurality of patterns and under the first porous insulation layer. | 03-05-2015 |
20150064885 | METHODS OF FORMING SEMICONDUCTOR DEVICES INCLUDING VERTICAL CHANNELS AND SEMICONDUCTOR DEVICES FORMED USING SUCH METHODS - Methods of forming semiconductor devices including vertical channels and semiconductor devices formed using such methods are provided. The methods may include forming a stack including a plurality of insulating patterns alternating with a plurality of conductive patterns on an upper surface of a substrate and forming a hole through the stack. The hole may expose sidewalls of the plurality of insulating patterns and the plurality of conductive patterns. The sidewalls of the plurality of insulating patterns may be aligned along a first plane that is slanted with respect to the upper surface of the substrate, and midpoints of the respective sidewalls of the plurality of conductive patterns may be aligned along a second plane that is substantially perpendicular to the upper surface of the substrate. | 03-05-2015 |
Patent application number | Description | Published |
20080253190 | Non-volatile memory device and method of operating the same - The present invention is directed to a non-volatile memory device and a method of operating the same. The non-volatile memory device includes a first transistor connected to an nth bitline and a second transistor connected to an (n+1)th bitline. The first transistor and the second transistor are serially coupled between the nth bitline and the (n+1)th bitline. The non-volatile memory device may include a 2-transistor 1-bit unit cell where a drain region and a source region of a memory cell have the same or similar structure. Since a cell array of a non-volatile memory device according to the invention may include a 2-transistor 2-bit unit cell, storage capacity of the non-volatile memory device may be doubled. | 10-16-2008 |
20100265765 | Non-volatile semiconductor memory device in which program disturb is reduced and method of programming the same - A non-volatile semiconductor memory device capable of reducing program disturb and a method of programming the same are provided. A bit line connected to a non-selected memory cell in the same block as a selected memory cell enters a floating state by inactivating a bit line selection switch, so that voltage levels of an first conductivity type channel and a source/drain terminal formed in a pocket second conductivity type well below a memory transistor have an intermediate level of a voltage level of a selection line and the pocket P type well. Therefore, program disturb caused by FN tunneling and junction hot electrons can be inhibited. | 10-21-2010 |
20120007212 | SEMICONDUCTOR DEVICE HAVING A DIODE - Provided is a semiconductor device. The semiconductor device includes a lower active region on a semiconductor substrate. A plurality of upper active regions protruding from a top surface of the lower active region and having a narrower width than the lower active region are provided. A lower isolation region surrounding a sidewall of the lower active region is provided. An upper isolation region formed on the lower isolation region, surrounding sidewalls of the upper active regions, and having a narrower width than the lower isolation region is provided. A first impurity region formed in the lower active region and extending into the upper active regions is provided. Second impurity regions formed in the upper active regions and constituting a diode together with the first impurity region are provided. A method of fabricating the same is provided as well. | 01-12-2012 |
20120018797 | NONVOLATILE MEMORY DEVICE, AND METHODS OF MANUFACTURING AND DRIVING THE SAME - A nonvolatile memory device includes a device isolation film defining an active region in a semiconductor substrate, a pocket well region formed in an upper portion of the active region and having a first conductivity type, a gate electrode formed on the active region and extending to intersect the active region, a tunnel insulating film, a charge storage film, and a blocking insulating film sequentially disposed between the active region and the gate electrode, a source region and a drain region respectively formed in a first region and a second region of the active region exposed on both sides of the gate electrode, and each having a second conductivity type opposite to the first conductivity type, a pocket well junction region formed in the first region adjacent to the source region and contacting the pocket well region, and having the first conductivity type, and a metal silicide layer formed in the first region and contacting the source region and the pocket well junction region. | 01-26-2012 |
20120070949 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING SEMICONDUCTOR DEVICE - A method of fabricating a semiconductor device includes providing a substrate having a memory block and a logic block defined therein, forming a dummy gate pattern on the memory block; forming a first region of a first conductivity type at one side of the dummy gate pattern and a second region of a second conductivity type at the other side of the dummy gate pattern, and forming a nonvolatile memory device electrically connected to the first region. | 03-22-2012 |
20120087189 | Non-Volatile Memory Device - A non-volatile memory device includes a first sector including a first sector selection transistor and a first plurality of pages connected to the first sector selection transistor, and a second sector including a second sector selection transistor and a second plurality of pages connected to the second sector selection transistor. Each of the first and second plurality of pages includes a memory transistor and a selection transistor, and a number of pages in the first plurality of pages is greater than a number of pages in the second plurality of pages. | 04-12-2012 |
20130308382 | NON-VOLATILE MEMORY DEVICE - A non-volatile memory device includes a first sector including a first sector selection transistor and a first plurality of pages connected to the first sector selection transistor, and a second sector including a second sector selection transistor and a second plurality of pages connected to the second sector selection transistor. Each of the first and second plurality of pages includes a memory transistor and a selection transistor, and a number of pages in the first plurality of pages is greater than a number of pages in the second plurality of pages. | 11-21-2013 |
20140217490 | NONVOLATILE MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - In a nonvolatile memory device and a method for fabricating the same, a device comprises a substrate, a trench in the substrate and a first gate pattern comprising a first bottom gate electrode having a first portion in the trench and having a second portion on the first portion and protruding in an upward direction relative to an upper surface of the substrate. A second gate pattern comprising a second gate electrode is on the substrate at a side of the first gate pattern and insulated from the first gate pattern. An impurity region is present in the substrate at a side of the first gate pattern opposite the second gate pattern, and overlapping part of the trench. | 08-07-2014 |
20140269064 | SOURCE LINE FLOATING CIRCUITS, MEMORY DEVICES INCLUDING THE SAME AND METHODS OF READING DATA IN A MEMORY DEVICE - A source line floating circuit includes a plurality of floating units. The floating units directly receive decoded row address signals or voltages of word lines as floating control signals, respectively. The decoded row address signals are activated selectively in response to a row address signal. The floating units control electrical connections between source lines and a source voltage in response to the floating control signals in a read operation. Related devices and methods are also described. | 09-18-2014 |
20150155024 | MAGNETIC MEMORY DEVICES INCLUDING SHARED LINES - A magnetic memory device includes word lines, bit lines intersecting the word lines, magnetic memory elements disposed at intersections between the word lines and the bit lines, and selection transistors connected to the word lines. The magnetic memory elements share a word line among the plurality of word lines and also share a selection transistor connected to the word line that is shared among the selection transistors. Related systems and operating methods are also described. | 06-04-2015 |
20150179244 | Magnetic Memory Devices Including Magnetic Memory Cells Having Opposite Magnetization Directions - A magnetic memory device includes first and second magnetic memory cells coupled to first and second bit lines, respectively. The first and second magnetic memory cells respectively include a pinned magnetic layer, a free magnetic layer, and a tunnel insulating layer therebetween. Respective stacking orders of the pinned magnetic layer, the tunnel insulating layer, and the free magnetic layer are different in the first and second magnetic memory cells. The magnetic memory device further includes at least one transistor that is configured to couple the first and second magnetic memory cells to a common source line. Related methods of operation are also discussed. | 06-25-2015 |
20160126289 | SEMICONDUCTOR DEVICE INCLUDING MAGNETO-RESISTIVE DEVICE - A semiconductor device comprises a magneto-resistive device capable of performing multiple functions with low power. The semiconductor device comprises a cell transistor in which a first impurity region and a second impurity region are respectively arranged on both sides of a channel region in a channel direction, a source line connected to the first impurity region of the cell transistor, and the magneto-resistive device connected to the second impurity region of the cell transistor. The first impurity region and the second impurity region are asymmetrical about a center of the cell transistor in the channel direction with respect to at least one of a shape and an impurity concentration distribution. | 05-05-2016 |
Patent application number | Description | Published |
20140159194 | SEMICONDUCTOR DEVICE - A semiconductor device includes a substrate having a plurality of active regions defined by a device isolation region, a plurality of conductive patterns on the plurality of active regions, each of the conductive patterns having side walls, a conductive line that faces the side walls of the conductive patterns with an air spacer therebetween on the active regions, the conductive line extending in a first direction, and a first insulating film covering the side walls of the conductive patterns between the air spacer and the conductive pattern. A lower portion of the first insulating film that is near the substrate protrudes toward the air spacer. | 06-12-2014 |
20140206186 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes forming a plurality of conductive lines separated from one another in a first direction via a slender hole and extending in a second direction perpendicular to the first direction, forming a first insulation layer filling the slender hole between the plurality of conductive lines, forming a plurality of first isolated holes separated from one another between the plurality of conductive lines in the first direction and the second direction by patterning the first insulation layer, forming a liner layer in the first isolated holes, filling a second insulation layer having an etching selectivity with respect to the first insulation layer, in the first isolated holes on the liner layer and forming a plurality of second isolated holes between the conductive lines by removing the first insulation layer using the etching selectivity between the second insulation layer and the first insulation layer. | 07-24-2014 |
20140231892 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME - First dopant regions and second dopant regions are provided at both sides of the gate structures. Conductive lines cross over the gate structures and are connected to the first dopant regions. Each of the conductive lines includes a conductive pattern and a capping pattern disposed on the conductive pattern. Contact structures are provided between the conductive lines and are connected to the second dopant regions. Each of the contact structures includes a lower contact pattern disposed on the second dopant region and an upper contact pattern disposed on the lower contact pattern. A bottom surface of the upper contact pattern is lower than a top surface of the conductive pattern. | 08-21-2014 |
20140264953 | WIRING STRUCTURES, METHODS OF MANUFACTURING THE SAME, AND METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES HAVING THE SAME - A method of manufacturing a wiring structure may include forming a first conductive pattern on a substrate, forming a hardmask on the first conductive pattern, forming a first spacer on sidewalls of the first conductive pattern and the hardmask, forming a first sacrificial layer pattern on a sidewall of the first spacer, forming a second spacer on a sidewall of the first sacrificial layer pattern, removing the first sacrificial layer pattern, and forming a third spacer on the second spacer, may be provided. The third spacer may contact an upper portion of the sidewall of the first spacer and define an air gap in association with the first and second spacers. The first spacer has a top surface substantially higher than a top surface of the first conductive pattern. The second spacer has a top surface substantially lower than the top surface of the first spacer. | 09-18-2014 |