| Patent application number | Description | Published |
|---|
| 20090101983 | Method of Achieving Dense-Pitch Interconnect Patterning in Integrated Circuits - Components in integrated circuits (ICs) are fabricated as small as possible to minimize sizes of the ICs and thus reduce manufacturing costs per IC. Metal interconnect lines are formed on minimum pitches possible using available photolithographic printers. Minimum pitches possible for contacts and vias are larger than minimum pitches possible for metal interconnect lines, thus preventing dense rectilinear grid configurations for contacts and vias. The instant invention is an integrated circuit, and a method of fabricating an integrated circuit, wherein metal interconnect lines are formed on a minimum pitch possible using a photolithographic printer. Contacts and vias are arranged to provide connections to components and metal interconnect lines, as required by the integrated circuit, in configurations that are compatible with the minimum pitch for contacts and vias, including semi-dense arrays. | 04-23-2009 |
| 20090125865 | SYSTEM AND METHOD FOR MAKING PHOTOMASKS - The present disclosure is directed a method for preparing photomask patterns. The method comprises receiving drawn pattern data for a design database. The drawn pattern data describes first device features and second device features, the second device features being associated with design specifications for providing a desired connectivity of the first device features to the second device features. At least a first plurality of the first device features have drawn patterns that will not result in sufficient coverage to effect the desired connectivity. Photomask patterns are formed for the first device features, wherein the photomask patterns for the first plurality of the first device features will result in the desired coverage. Integrated circuit devices formed using the principles of the present disclosure are also taught. | 05-14-2009 |
| 20090300567 | DESIGN LAYOUT OF PRINTABLE ASSIST FEATURES TO AID TRANSISTOR CONTROL - Exemplary embodiments provide a method for laying out an IC design and the IC design layout. The IC design layout can include one or more gate features placed on an active region including a first pitch (p | 12-03-2009 |
| 20100031216 | METHOD FOR LAYOUT OF RANDOM VIA ARRAYS IN THE PRESENCE OF STRONG PITCH RESTRICTIONS - Exemplary embodiments provide a method for laying out an integrated circuit (“IC”) design and the IC design layout. In one embodiment, the IC design layout can include a first feature placed on a first intersecting point of a grid. The placed first feature can define a local grid area. The local grid area can further include a plurality of local intersecting points having an outer perimeter spaced from any outermost local intersecting point in a spacing ranging from a length of a grid side to a length of a grid diagonal of a grid unit. A second feature can either be restrictively placed on any local intersecting point of the local grid area, or be randomly placed on any location outside the outer perimeter of the local grid area. | 02-04-2010 |
| 20100167484 | Gate line edge roughness reduction by using 2P/2E process together with high temperature bake - A method of patterning a plurality of polysilicon structures includes forming a polysilicon layer over a semiconductor body, and patterning the polysilicon layer to form a first polysilicon structure using a first patterning process that reduces line-edge roughness (LER). The method further includes patterning the polysilicon layer to form a second polysilicon structure using a second patterning process that is different from the first patterning process after performing the first patterning process. | 07-01-2010 |
| 20100167513 | DUAL ALIGNMENT STRATEGY FOR OPTIMIZING CONTACT LAYER ALIGNMENT - An improved method for optimizing layer registration during lithography in the fabrication of a semiconductor device is disclosed. In one example, the method comprises optimizing contact layer registration of an SRAM device having a plurality of transistors having active and gate region features extending generally along a channel length (X) direction and a channel width (Y) direction, respectively. The method comprises aligning a contact layer to a gate layer in the channel length direction (X), using gate layer overlay marks to control the alignment of the contact layer in the channel length direction (X) of the semiconductor device. The method further includes aligning the contact layer to an active layer in the channel width direction (Y), using active layer overlay marks to control the alignment of the contact layer in the channel width direction (Y) of the semiconductor device. | 07-01-2010 |
