Patent application number | Description | Published |
20150134935 | Split Register File for Operands of Different Sizes - In an embodiment, a processor includes a register file having multiple widths corresponding to different operands sizes of a given data type implemented by the processor. For example, the integer register file may have 32 bit and 64 bit widths for 32 and 64 bit operand sizes. The register file may have a section of registers for each operand size, and the map unit may allocate registers from the appropriate section for each instruction operation based on the operand size of that instruction operation. The register file may consume less integrated circuit area than another register file having the same number of registers, all of which are implemented at the largest operand size. In some embodiments, only the register file and the map unit (specifically the free list management logic in the map unit) are changed to implement the multiple-width register file. | 05-14-2015 |
20150227374 | EARLY LOOP BUFFER ENTRY - Systems, processors, and methods for determining when to enter loop buffer mode early for loops in an instruction stream. A processor waits until a branch history register has saturated before entering loop buffer mode for a loop if the processor has not yet determined the loop has an unpredictable exit. However, if the loop has an unpredictable exit, then the loop is allowed to enter loop buffer mode early. While in loop buffer mode, the loop is dispatched from a loop buffer, and the front-end of the processor is powered down until the loop terminates. | 08-13-2015 |
20160085550 | IMMEDIATE BRANCH RECODE THAT HANDLES ALIASING - A system and method for efficiently indicating branch target addresses. A semiconductor chip predecodes instructions of a computer program prior to installing the instructions in an instruction cache. In response to determining a particular instruction is a control flow instruction with a displacement relative to a program counter address (PC), the chip replaces a portion of the PC relative displacement in the particular instruction with a subset of a target address. The subset of the target address is an untranslated physical subset of the full target address. When the recoded particular instruction is fetched and decoded, the remaining portion of the PC relative displacement is added to a virtual portion of the PC used to fetch the particular instruction. The result is concatenated with the portion of the target address embedded in the fetched particular instruction to form a full target address. | 03-24-2016 |
20160092236 | MECHANISM FOR ALLOWING SPECULATIVE EXECUTION OF LOADS BEYOND A WAIT FOR EVENT INSTRUCTION - A processor includes a mechanism that checks for and flushes only speculative loads and any respective dependent instructions that are younger than an executed wait for event (WEV) instruction, and which also match an address of a store instruction that has been determined to have been executed by a different processor prior to execution of the paired SEV instruction by the different processor. The mechanism may allow speculative loads that do not match the address of any store instruction that has been determined to have been executed by a different processor prior to execution of the paired SEV instruction by the different processor. | 03-31-2016 |
Patent application number | Description | Published |
20120220600 | N-Oxide of 3-(2,6-dichloro-3,5-dimethoxy-phenyl) -1--1-methyl-urea - An N-oxide of 3-(2,6-Dichloro-3,5-dimethoxy-phenyl)-1-{6-[4-(4-ethyl-piperazin-1-yl)-phenylamino]-pyrimidin-4-yl}-1-methyl-urea, pharmaceutically acceptable salts thereof, compositions including the compound and its pharmaceutically acceptable salts, and methods of preparing the compound and the compositions (such as, for example, by oxidizing 3-(2,6-Dichloro-3,5-dimethoxy-phenyl)-1-{6-[4-(4-ethyl-piperazin-1-yl)-phenylamino]-pyrimidin-4-yl}-1-methyl-urea with an oxidizing agent) are described. Further described herein are methods of using the compound and compositions of the present technology, alone and in combination with other suitable agents, to treat various diseases, including but not limited to, those that can be prevented, inhibited or ameliorated by inhibition of kinase activity selected from FGFR1, FGFR2, FGFR3 or FGFR4. | 08-30-2012 |
20140378468 | N-Oxide of 3-(2,6-dichloro-3,5-dimethoxy-phenyl)-1--1-methyl-urea - An N-oxide of 3-(2,6-Dichloro-3,5-dimethoxy-phenyl)-1-{6-[4-(4-ethyl-piperazin-1-yl)-phenylamino]pyrimidin-4-yl}-1-methyl-urea, pharmaceutically acceptable salts thereof, compositions including the compound and its pharmaceutically acceptable salts, and methods of preparing the compound and the compositions (such as, for example, by oxidizing 3-(2,6-Dichloro-3,5-dimethoxy-phenyl)-1-{6-[4-(4-ethyl-piperazin-1-yl)-phenylamino]-pyrimidin-4-yl}-1-methyl-urea with an oxidizing agent) are described. Further described herein are methods of using the compound and compositions of the present technology, alone and in combination with other suitable agents, to treat various diseases, including but not limited to, those that can be prevented, inhibited or ameliorated by inhibition of kinase activity selected from FGFR1, FGFR2, FGFR3 or FGFR4. | 12-25-2014 |
20160102062 | N-Oxide of 3-(2,6-dichloro-3,5-dimethoxy-phenyl)-1--1-methyl-urea - An N-oxide of 3-(2,6-Dichloro-3,5-dimethoxy-phenyl)-1-{6-[4-(4-ethyl-piperazin-1-yl)-phenylamino]-pyrimidin-4-yl}-1-methyl-urea, pharmaceutically acceptable salts thereof, compositions including the compound and its pharmaceutically acceptable salts, and methods of preparing the compound and the compositions (such as, for example, by oxidizing 3-(2,6-Dichloro-3,5-dimethoxy-phenyl)-1-{6-[4-(4-ethyl-piperazin-1-yl)-phenylamino]-pyrimidin-4-yl}-1-methyl-urea with an oxidizing agent) are described. Further described herein are methods of using the compound and compositions of the present technology, alone and in combination with other suitable agents, to treat various diseases, including but not limited to, those that can be prevented, inhibited or ameliorated by inhibition of kinase activity selected from FGFR1, FGFR2, FGFR3 or FGFR4. | 04-14-2016 |
Patent application number | Description | Published |
20090203222 | METHOD OF FORMING DIELECTRIC FILMS, NEW PRECURSORS AND THEIR USE IN SEMICONDUCTOR MANUFACTURING - Method of deposition on a substrate, of a metal containing dielectric film comprising a compound of the formula (I): | 08-13-2009 |
20090311879 | METHOD OF FORMING HIGH-K DIELECTRIC FILMS BASED ON NOVEL TITANIUM, ZIRCONIUM, AND HAFNIUM PRECURSORS AND THEIR USE FOR SEMICONDUCTOR MANUFACTURING - A method of forming on at least one support at least one metal containing dielectric films having the formula (M | 12-17-2009 |
20100055310 | GROUP V METAL CONTAINING PRECURSORS AND THEIR USE FOR METAL CONTAINING FILM DEPOSITION - Compound of the formula (Ia), or of the formula (Ib). These new precursors are useful for pure metal, metallic oxide, oxynitride, nitride and/or silicide film deposition to make electrodes and/or high k layers, and/or copper diffusion barrier layers, etc. | 03-04-2010 |
20110195574 | NIOBIUM AND VANADIUM ORGANOMETALLIC PRECURSORS FOR THIN FILM DEPOSITION - Compound of the formula Cp(R | 08-11-2011 |
20110207337 | METHOD OF FORMING DIELECTRIC FILMS, NEW PRECURSORS AND THEIR USE IN SEMICONDUCTOR MANUFACTURING - The application relates to a method of deposition on a substrate, of a metal containing dielectric film comprising a compound of the formula (M | 08-25-2011 |
20110244681 | METHOD OF FORMING A TANTALUM-CONTAINING LAYER ON A SUBSTRATE - A method for forming a tantalum-containing layer on a substrate, the method comprising at least the steps of:
| 10-06-2011 |
20110275215 | METHOD FOR FORMING A TITANIUM-CONTAINING LAYER ON A SUBSTRATE USING AN ATOMIC LAYER DEPOSITION (ALD) PROCESS - A method for forming a titanium-containing layer on a substrate, the method comprising at least the steps of: a) providing a vapor comprising at least one precursor compound of the formula Ti(Me | 11-10-2011 |
20140242812 | METHOD OF FORMING DIELECTRIC FILMS, NEW PRECURSORS AND THEIR USE IN SEMICONDUCTOR MANUFACTURING - Method of deposition on a substrate of a dielectric film by introducing into a reaction chamber a vapor of a precursor selected from the group consisting of Zr(MeCp)(NMe | 08-28-2014 |