Blake, Jr.
Arthur J. Blake, Jr., Leominster, MA US
Patent application number | Description | Published |
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20120268106 | SMART CURRENT TRANSFORMERS - According to one aspect, embodiments of the invention provide a current monitoring device comprising a current transformer configured to be removeably coupled to a power line and to generate a reference signal having a level related to a current level of the power line, a sensor circuit connected to the current transformer and configured to be removeably coupled to a communications bus and to convert the reference signal to a digital reference signal and provide a signal indicative of the current level to the communication bus, and a housing containing the sensor circuit and the current transformer. | 10-25-2012 |
Arthur Joseph Blake, Jr., Leominster, MA US
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20150102803 | CURRENT MONITORING DEVICE - According to one aspect, embodiments of the invention provide a current monitoring device comprising a current transformer configured to be removeably coupled to a power line and to generate a reference signal having a level related to a current level of the power line, a sensor circuit connected to the current transformer and configured to convert the reference signal to a measurement signal, a flexible cable having a first end and a second end, the first end coupled to the sensor circuit, and a connection portion coupled to the second end of the flexible cable and configured to be removeably coupled to a communications bus, wherein the sensor circuit is further configured to provide the measurement signal to the communication bus via the flexible cable and the connection portion. | 04-16-2015 |
Carl C. Blake, Jr., Fountain Valley, CA US
Patent application number | Description | Published |
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20110193619 | SEMICONDUCTOR ELECTRONIC COMPONENTS AND CIRCUITS - An electronic component includes a high-voltage depletion-mode transistor and a low-voltage enhancement-mode transistor both encased in a single package. A source electrode of the high-voltage depletion-mode transistor is electrically connected to a drain electrode of the low-voltage enhancement-mode transistor, a drain electrode of the high-voltage depletion-mode transistor is electrically connected to a drain lead of the single package, a gate electrode of the low-voltage enhancement-mode transistor is electrically connected to a gate lead of the single package, a gate electrode of the high-voltage depletion-mode transistor is electrically connected to an additional lead of the single package, and a source electrode of the low-voltage enhancement-mode transistor is electrically connected to a conductive structural portion of the single package. | 08-11-2011 |
20140042495 | SEMICONDUCTOR ELECTRONIC COMPONENTS AND CIRCUITS - An electronic component includes a high-voltage depletion-mode transistor and a low-voltage enhancement-mode transistor both encased in a single package. A source electrode of the high-voltage depletion-mode transistor is electrically connected to a drain electrode of the low-voltage enhancement-mode transistor, a drain electrode of the high-voltage depletion-mode transistor is electrically connected to a drain lead of the single package, a gate electrode of the low-voltage enhancement-mode transistor is electrically connected to a gate lead of the single package, a gate electrode of the high-voltage depletion-mode transistor is electrically connected to an additional lead of the single package, and a source electrode of the low-voltage enhancement-mode transistor is electrically connected to a conductive structural portion of the single package. | 02-13-2014 |
Daniel R. Blake, Jr., Chicago, IL US
Patent application number | Description | Published |
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20120074024 | STACKABLE STORAGE BIN - A stackable storage bin includes a body having a rim extending around an open top. A first angled slot is formed in an upper edge of each side wall adjacent a rear end thereof and a vertical second slot is formed in the upper edge of each side wall at a position forwardly from the first slot. An angled first tab is formed adjacent the bottom edge of each side wall in a position vertically aligned with the first slot and a vertical second tab is formed adjacent a bottom edge of each side wall at a position vertically aligned with the vertical second slot whereby when two of the bins are in the vertically stacked array, the tabs on the bottom of an upper bin engage the slots on the lower bin to interlock the two bins together. | 03-29-2012 |