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Blainey

Paul Blainey, Mountain View, CA US

Patent application numberDescriptionPublished
20100069250Digital PCR Calibration for High Throughput Sequencing - Disclosed is a method for accurately determining the number of template molecules in a library of nucleic acids (e.g., DNA) to be sequenced. The method does not require large amounts of the DNA sample, nor does it require the preparation of a standard curve. The method is especially applicable to methodologies for “sequencing by synthesis,” where quantitation of the starting library is important. The method uses quantitative real time PCR, especially digital PCR, which measures the number of individual molecules in a sample. The present method particularly may use a microfluidic device for running large numbers of PCR reactions. Each PCR reaction is monitored in real time by a primer/probe combination. The forward primer is adapted to contain a sequence not on the adapter but which corresponds to a probe sequence. A short probe which generates fluorescence during the PCR process is used.03-18-2010

Robert J. Blainey, Newmarket CA

Patent application numberDescriptionPublished
20090217018METHODS, APPARATUS AND ARTICLES OF MANUFACTURE FOR REGAINING MEMORY CONSISTENCY AFTER A TRAP VIA TRANSACTIONAL MEMORY - Embodiments of the invention provide a method for regaining memory consistency after a trap via transactional memory. Transactional memory and a transactional memory log are used to undo changes made to memory from a transaction start point up to the point of a trap event. After the trap event is processed, and the changes are rolled back, the program can resume execution at the beginning of the transaction.08-27-2009
20100174840PRIORITIZATION FOR CONFLICT ARBITRATION IN TRANSACTIONAL MEMORY MANAGEMENT - Embodiments of the present invention provide a method, system and computer program product for software prioritization of concurrent transactions for embedded conflict arbitration in transactional memory management. In an embodiment of the invention, a method for software prioritization of concurrent transactions for embedded conflict arbitration in transactional memory management can include setting different hardware registers with different priority values for correspondingly different transactions in a transactional memory system configured for transactional memory management according to respective priority values specified by priority assignment logic in external software support for the system. The method also can include detecting a conflict amongst the transactions in the system. Finally, the method can include applying conflict arbitration within the system based upon the priority values specified by the priority assignment logic in the external software support for the system.07-08-2010
20100174874DYNAMIC NEST LEVEL DETERMINATION FOR NESTED TRANSACTIONAL MEMORY ROLLBACK - Embodiments of the present invention address deficiencies of the art in respect to nested transaction rollback and provide a method, system and computer program product for dynamic nest level determination for nested transaction rollback. In an embodiment of the invention, a nested transaction rollback method can be provided. The method can include detecting a violation of a block of memory accessed within a set of nested transactions, retrieving a tentative rollback level for the violation, discarding a speculative state for the block of memory at each level of the set of nested transactions up to and including the tentative rollback level, refining the tentative rollback level to a lower level in the set of nested transactions, and additionally discarding a speculative state for the block of memory at additional levels in the set of nested transactions up to and including the refined rollback level.07-08-2010

Patent applications by Robert J. Blainey, Newmarket CA

Robert James Blainey, Newmarket CA

Patent application numberDescriptionPublished
20090217104METHOD AND APPARATUS FOR DIAGNOSTIC RECORDING USING TRANSACTIONAL MEMORY08-27-2009
20100095271Fine-Grained Software-Directed Data Prefetching Using Integrated High-Level and Low-Level Code Analysis Optimizations - A mechanism for minimizing effective memory latency without unnecessary cost through fine-grained software-directed data prefetching using integrated high-level and low-level code analysis and optimizations is provided. The mechanism identifies and classifies streams, identifies data that is most likely to incur a cache miss, exploits effective hardware prefetching to determine the proper number of streams to be prefetched, exploits effective data prefetching on different types of streams in order to eliminate redundant prefetching and avoid cache pollution, and uses high-level transformations with integrated lower level cost analysis in the instruction scheduler to schedule prefetch instructions effectively.04-15-2010

Patent applications by Robert James Blainey, Newmarket CA