Patent application number | Description | Published |
20090217018 | METHODS, APPARATUS AND ARTICLES OF MANUFACTURE FOR REGAINING MEMORY CONSISTENCY AFTER A TRAP VIA TRANSACTIONAL MEMORY - Embodiments of the invention provide a method for regaining memory consistency after a trap via transactional memory. Transactional memory and a transactional memory log are used to undo changes made to memory from a transaction start point up to the point of a trap event. After the trap event is processed, and the changes are rolled back, the program can resume execution at the beginning of the transaction. | 08-27-2009 |
20100174840 | PRIORITIZATION FOR CONFLICT ARBITRATION IN TRANSACTIONAL MEMORY MANAGEMENT - Embodiments of the present invention provide a method, system and computer program product for software prioritization of concurrent transactions for embedded conflict arbitration in transactional memory management. In an embodiment of the invention, a method for software prioritization of concurrent transactions for embedded conflict arbitration in transactional memory management can include setting different hardware registers with different priority values for correspondingly different transactions in a transactional memory system configured for transactional memory management according to respective priority values specified by priority assignment logic in external software support for the system. The method also can include detecting a conflict amongst the transactions in the system. Finally, the method can include applying conflict arbitration within the system based upon the priority values specified by the priority assignment logic in the external software support for the system. | 07-08-2010 |
20100174874 | DYNAMIC NEST LEVEL DETERMINATION FOR NESTED TRANSACTIONAL MEMORY ROLLBACK - Embodiments of the present invention address deficiencies of the art in respect to nested transaction rollback and provide a method, system and computer program product for dynamic nest level determination for nested transaction rollback. In an embodiment of the invention, a nested transaction rollback method can be provided. The method can include detecting a violation of a block of memory accessed within a set of nested transactions, retrieving a tentative rollback level for the violation, discarding a speculative state for the block of memory at each level of the set of nested transactions up to and including the tentative rollback level, refining the tentative rollback level to a lower level in the set of nested transactions, and additionally discarding a speculative state for the block of memory at additional levels in the set of nested transactions up to and including the refined rollback level. | 07-08-2010 |
20120166747 | DYNAMIC NEST LEVEL DETERMINATION FOR NESTED TRANSACTIONAL MEMORY ROLLBACK - Embodiments of the present invention address deficiencies of the art in respect to nested transaction rollback and provide a method, system and computer program product for dynamic nest level determination for nested transaction rollback. In an embodiment of the invention, a nested transaction rollback method can be provided. The method can include detecting a violation of a block of memory accessed within a set of nested transactions, retrieving a tentative rollback level for the violation, discarding a speculative state for the block of memory at each level of the set of nested transactions up to and including the tentative rollback level, refining the tentative rollback level to a lower level in the set of nested transactions, and additionally discarding a speculative state for the block of memory at additional levels in the set of nested transactions up to and including the refined rollback level. | 06-28-2012 |
20130086338 | LINKING CODE FOR AN ENHANCED APPLICATION BINARY INTERFACE (ABI) WITH DECODE TIME INSTRUCTION OPTIMIZATION - A code sequence made up multiple instructions and specifying an offset from a base address is identified in an object file. The offset from the base address corresponds to an offset location in a memory configured for storing an address of a variable or data. The identified code sequence is configured to perform a memory reference function or a memory address computation function. It is determined that the offset location is within a specified distance of the base address and that a replacement of the identified code sequence with a replacement code sequence will not alter program semantics. The identified code sequence in the object file is replaced with the replacement code sequence that includes a no-operation (NOP) instruction or having fewer instructions than the identified code sequence. Linked executable code is generated based on the object file and the linked executable code is emitted. | 04-04-2013 |
20130086369 | COMPILING CODE FOR AN ENHANCED APPLICATION BINARY INTERFACE (ABI) WITH DECODE TIME INSTRUCTION OPTIMIZATION - Compiling code for an enhanced application binary interface (ABI) including identifying, by a computer, a code sequence configured to perform a variable address reference table function including an access to a variable at an offset outside of a location in a variable address reference table. The code sequence includes an internal representation (IR) of a first instruction and an IR of a second instruction. The second instruction is dependent on the first instruction. A scheduler cost function associated with at least one of the IR of the first instruction and the IR of the second instruction is modified. The modifying includes generating a modified scheduler cost function that is configured to place the first instruction next to the second instruction. An object file is generated responsive to the modified scheduler cost function. The object file includes the first instruction placed next to the second instruction. The object file is emitted. | 04-04-2013 |
20130086563 | COMPILING CODE FOR AN ENHANCED APPLICATION BINARY INTERFACE (ABI) WITH DECODE TIME INSTRUCTION OPTIMIZATION - A code sequence made up multiple instructions and specifying an offset from a base address is identified in an object file. The offset from the base address corresponds to an offset location in a memory configured for storing an address of a variable or data. The identified code sequence is configured to perform a memory reference function or a memory address computation function. It is determined that the offset location is within a specified distance of the base address and that a replacement of the identified code sequence with a replacement code sequence will not alter program semantics. The identified code sequence in the object file is replaced with the replacement code sequence that includes a no-operation (NOP) instruction or having fewer instructions than the identified code sequence. Linked executable code is generated based on the object file and the linked executable code is emitted. | 04-04-2013 |
20130086570 | LINKING CODE FOR AN ENHANCED APPLICATION BINARY INTERFACE (ABI) WITH DECODE TIME INSTRUCTION OPTIMIZATION - A code sequence made up multiple instructions and specifying an offset from a base address is identified in an object file. The offset from the base address corresponds to an offset location in a memory configured for storing an address of a variable or data. The identified code sequence is configured to perform a memory reference function or a memory address computation function. It is determined that the offset location is within a specified distance of the base address and that a replacement of the identified code sequence with a replacement code sequence will not alter program semantics. The identified code sequence in the object file is replaced with the replacement code sequence that includes a no-operation (NOP) instruction or having fewer instructions than the identified code sequence. Linked executable code is generated based on the object file and the linked executable code is emitted. | 04-04-2013 |
20130318510 | COMPILING CODE FOR AN ENHANCED APPLICATION BINARY INTERFACE (ABI) WITH DECODE TIME INSTRUCTION OPTIMIZATION - Generating decode time instruction optimization (DTIO) object code that enables a DTIO enabled processor to optimize execution of DTIO instructions. A code sequence configured to facilitate DTIO in a DTIO enabled processor is identified by a computer. The code sequence includes an internal representation (IR) of a first instruction and an IR of a second instruction. The second instruction is dependent on the first instruction. A schedule associated with at least one of the IR of the first instruction and the IR of the second instruction is modified. The modifying includes generating a modified schedule that is configured to place the first instruction next to the second instruction. An object file is generated based on the modified schedule. The object file includes the first instruction placed next to the second instruction. The object file is emitted. | 11-28-2013 |