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Bjoerk
Mikael Bjoerk, Affoltern Am Albis CH
| Patent application number | Description | Published |
|---|---|---|
| 20110315953 | METHOD OF FORMING COMPOUND SEMICONDUCTOR - A method of forming a semiconductor is provided and includes patterning a pad and a nanowire onto a wafer, the nanowire being substantially perpendicular with a pad sidewall and substantially parallel with a wafer surface and epitaxially growing on an outer surface of the nanowire a secondary layer of semiconductor material, which is lattice mismatched with respect to a material of the nanowire and substantially free of defects. | 12-29-2011 |
Mikael T. Bjoerk, Rueschlikon CH
| Patent application number | Description | Published |
|---|---|---|
| 20110049474 | TUNNEL FIELD EFFECT DEVICES - An indirectly induced tunnel emitter for a tunneling field effect transistor (TFET) structure includes an outer sheath that at least partially surrounds an elongated core element, the elongated core element formed from a first semiconductor material; an insulator layer disposed between the outer sheath and the core element; the outer sheath disposed at a location corresponding to a source region of the TFET structure; and a source contact that shorts the outer sheath to the core element; wherein the outer sheath is configured to introduce a carrier concentration in the source region of the core element sufficient for tunneling into a channel region of the TFET structure during an on state. | 03-03-2011 |
Mikael T. Bjoerk, Zurich CH
| Patent application number | Description | Published |
|---|---|---|
| 20110049476 | IMPACT IONIZATION FIELD-EFFECT TRANSISTOR - An Impact Ionization Field-Effect Transistor (I-MOS) device in which device degradation caused by hot carrier injection into a gate oxide is prevented. The device includes source, drain, and gate contacts, and a channel between the source and the drain. The channel has a dimension normal to the direction of a charge carrier transport in the channel such that the energy separation of the first two sub-bands equals or exceeds the effective energy band gap of the channel material. | 03-03-2011 |
Mikael T. Bjoerk, Affoltern Am Albis CH
| Patent application number | Description | Published |
|---|---|---|
| 20100072460 | NANOELECTRONIC DEVICE - An electronic device and method of manufacturing the device. The device includes a semiconducting region, which can be a nanowire, a first contact electrically coupled to the semiconducting region, and at least one second contact capacitively coupled to the semiconducting region. At least a portion of the semiconducting region between the first contact and the second contact is covered with a dipole layer. The dipole layer can act as a local gate on the semiconducting region to enhance the electric properties of the device. | 03-25-2010 |
| 20110269302 | METHOD OF FABRICATING A SEMICONDUCTOR DEVICE - The invention relates to a method of fabricating a semiconductor device. The method includes: providing a semiconductor substrate and locally heating the semiconductor substrate by using a heated tip structure. Locally heating the semiconductor substrate is carried out to locally modify the electrical properties of the semiconductor substrate. The semiconductor substrate can be implanted with dopants, so that locally heating step causes a local activation of the implanted dopants. Furthermore, the semiconductor substrate can be provided with a dopant layer, so that locally heating step causes dopants to diffuse into the semiconductor substrate. | 11-03-2011 |
Mikael T. Bjoerk, Adliswil CH
| Patent application number | Description | Published |
|---|---|---|
| 20090146133 | HYBRID SEMICONDUCTOR STRUCTURE - A method for the fabrication of a semiconductor structure that includes areas that have different crystalline orientation and semiconductor structure formed thereby. The disclosed method allows fabrication of a semiconductor structure that has areas of different semiconducting materials. The method employs templated crystal growth using a Vapor-Liquid-Solid (VLS) growth process. A silicon semiconductor substrate having a first crystal orientation direction is etched to have an array of holes into its surface. A separation layer is formed on the inner surface of the hole for appropriate applications. A growth catalyst is placed at the bottom of the hole and a VLS crystal growth process is initiated to form a nanowire. The resultant nanowire crystal has a second different crystal orientation which is templated by the geometry of the hole. | 06-11-2009 |
| 20090200540 | Metal-Oxide-Semiconductor Device Including a Multiple-Layer Energy Filter - A MOS device includes first and second source/drains spaced apart relative to one another. A channel is formed in the device between the first and second source/drains. A gate is formed in the device between the first and second source/drains and proximate the channel, the gate being electrically isolated from the first and second source/drains and the channel. The gate is configured to control a conduction of the channel as a function of a potential applied to the gate. The MOS device further includes an energy filter formed between the first source/drain and the channel. The energy filter includes a superlattice structure wherein a mini-band is formed. The energy filter is operative to control an injection of carriers from the first source/drain into the channel. The energy filter, in combination with the first source/drain, is configured to produce an effective zero-Kelvin first source/drain. | 08-13-2009 |
| 20090200605 | Metal-Oxide-Semiconductor Device Including an Energy Filter - A MOS device includes first and second source/drains spaced apart relative to one another. A channel is formed in the device between the first and second source/drains. A gate is formed in the device between the first and second source/drains and proximate the channel, the gate being electrically isolated from the first and second source/drains and the channel. The gate is configured to control a conduction of the channel as a function of a potential applied to the gate. The MOS device further includes an energy filter formed between the first source/drain and the channel. The energy filter includes an impurity band operative to control an injection of carriers from the first source/drain into the channel. | 08-13-2009 |
| 20090273011 | Metal-Oxide-Semiconductor Device Including an Energy Filter - A MOS device includes first and second source/drains spaced apart relative to one another. A channel is formed in the device between the first and second source/drains. A gate is formed in the device between the first and second source/drains and proximate the channel, the gate being electrically isolated from the first and second source/drains and the channel. The gate is configured to control a conduction of the channel as a function of a potential applied to the gate. The MOS device further includes an energy filter formed between the first source/drain and the channel. The energy filter includes an impurity band operative to control an injection of carriers from the first source/drain into the channel. | 11-05-2009 |