| Patent application number | Description | Published |
|---|
| 20090103855 | Three-dimensional die stacks with inter-device and intra-device optical interconnect - Examples of a computer system packaged in a three-dimensional stack of dies are described. The package includes an electrical die and an optical die coupled to and stacked with the electrical die. The electrical die includes circuitry to process and communicate electrical signals, and the optical die includes structures to transport optical signals. The electrical die has a smaller area than the optical die so that the optical die includes an exposed mezzanine which is configured with optical input/output ports. Additionally, the packaging can be configured to provide structural support against insertion forces for external optical connections. | 04-23-2009 |
| 20090103929 | Synchronous optical bus providing communication between computer system components - A synchronous optical bus system for communication between computer system components is described. In one example, the optical bus system is used for communication between a memory controller and memory devices optically coupled to an optical interconnect. Optical bus interface units couple the components to the optical interconnect and are arranged on the optical interconnect in order that a sum of an optical path length from a controller component to each computer system component and from each computer system component to the controller component is the same for all the coupled computer system components. A synchronous protocol is used for communication between the components. | 04-23-2009 |
| 20110010525 | On-chip and Chip-to-chip Routing Using a Processor Element/Router Combination - A system and method is shown for on-chip and chip-to-chip routing. The system and method includes a processor element residing on a processor die to process a data packet received at the processor die. The system and method also include a router residing on the process die to route the data packet received at the processor die. Further, the system and method includes a switch core residing on the processor die to switch a communication channel along which the data packet is to be transmitted. Additionally, the system and method includes a switch core to identify a destination processing element and router (PE/R) module for a data packet, the switch core and the destination PE/R module residing on a common processor die. Moreover, the system and method includes a communication channel to operatively connect the switch core and the destination PE/R module on the common processor die. | 01-13-2011 |
| 20110052204 | Intentionally Skewed Optical Clock Signal Distribution - Embodiments of the present invention relate to systems and methods for distributing an intentionally skewed optical-clock signal to nodes of a source synchronous computer system. In one system embodiment, a source synchronous system comprises a waveguide, an optical-system clock optically coupled to the waveguide, and a number of nodes optically coupled to the waveguide. The optical-system clock generates and injects a master optical-clock signal into the waveguide. The master optical-clock signal acquiring a skew as it passes between nodes. Each node extracts a portion of the master optical-clock signal and processes optical signals using the portion of the master optical-clock signal having a different skew for the respective extracting node. | 03-03-2011 |
| 20110085561 | Incremental Adaptive Packet Routing In A Multi-Dimensional Network - Illustrated is a computer system and method that includes a Processing Element (PE) to generate a data packet that is routed along a shortest path that includes a plurality of routers in a multiple dimension network. The system and method further include a router, of the plurality of routers, to de-route the data packet from the shortest path to an additional path, the de-route to occur where the shortest path is congested and the additional path links the router and an additional router in a dimension of the multiple dimension network. | 04-14-2011 |
| Patent application number | Description | Published |
|---|
| 20090103854 | Photonic interconnects for computer system devices - Various embodiments of the present invention are directed to photonic interconnects that can be used for on-chip as well as off-chip communications between computer system components. In one embodiment of the present invention, a photonic interconnect comprises a plurality of on-chip waveguides. Additionally, the photonic interconnect may include a plurality of off-chip waveguides, and at least one optoelectronic converter. The at least one optoelectronic converter can be photonically coupled to a portion of the plurality of on-chip waveguides, can be photonically coupled to a portion of the plurality of off-chip waveguides, and is in electronic communication with at least one computer system component. | 04-23-2009 |
| 20090274413 | Photonic interconnects for computer system devices - Various embodiments of the present invention are directed to photonic interconnects that can be used for on-chip as well as off-chip communications between computer system components. In one embodiment of the present invention, a photonic interconnect comprises a plurality of on-chip waveguides. Additionally, the photonic interconnect may include a plurality of off-chip waveguides, and at least one optoelectronic converter. The at least one optoelectronic converter can be photonically coupled to a portion of the plurality of on-chip waveguides, can be photonically coupled to a portion of the plurality of off-chip waveguides, and is in electronic communication with at least one computer system component. | 11-05-2009 |
| 20110206377 | PRIORITIZED OPTICAL ARBITRATION SYSTEMS AND METHODS - Various embodiments of the present invention relate to systems and methods for achieving low-latency, prioritized, distributed optical-base arbitration. In one embodiment, an optical arbitration system ( | 08-25-2011 |
| 20110280569 | Integrated Circuit With Optical Interconnect - The present invention provides one or more embodiments of an optical interconnect design suitable for providing communication between computer system components in a computer system device. The optical interconnect ( | 11-17-2011 |
| 20110280579 | ENERGY-EFFICIENT AND FAULT-TOLERANT RESONATOR-BASED MODULATION AND WAVELENGTH DIVISION MULTIPLEXING SYSTEMS - Systems and methods are provided for modulating, channels in dense wavelength division multiplexing (“DWDM”) systems. In one aspect, a modulation and wavelength division multiplexing system includes a channel source and a waveguide tree structure disposed on a substrate. The tree structure includes waveguides branching from a root waveguide. The waveguides include two or more terminus waveguides coupled to the channel source. The system also includes one or more modulator arrays disposed on the substrate. Each modulator array is optically coupled to one of the two or more terminus waveguides and is configured to modulate channels injected into a terminus waveguide from the channel source to produce corresponding optical signals that propagate from the terminus waveguide along one or more of the waveguides to the root waveguide. | 11-17-2011 |
