Patent application number | Description | Published |
20080212251 | BATTERY PROTECTING CIRCUIT AND BATTERY WITH SUCH PROTECTING CIRCUIT - A protecting circuit for a battery used to power an electronic system includes a control circuit and a sensing circuit. The sensing circuit includes a tri-axial accelerometer having X, Y and Z axes. The tri-axial accelerometer is capable of detecting position changes of the battery and outputs through the X, Y and Z axes voltages that correspond to the position changes. The sensing circuit ultimately outputs a controlling voltage to the control circuit according to the voltages outputted by the X, Y and Z axes. When the battery is being installed onto or uninstalled from the electronic system, the outputted controlling voltage makes the control circuit OFF and the battery cannot power the electronic system. When the battery have been installed onto the electronic system, the outputted controlling voltage turns the control circuit ON and the battery can supply power to the electronic system. | 09-04-2008 |
20110208844 | CLUSTER SYSTEM, METHOD AND DEVICE FOR EXPANDING CLUSTER SYSTEM - A method for expanding a cluster system is provided. The cluster system includes at least one Cluster Central Chassis (CCC), and a newly-added Cluster Line-card Chassis (CLC) connected with the CCC to form the cluster system. The method includes the following steps. A control plane is established. An equipment management right is switched to the CCC, so that the CCC manages the newly-added CLC. Meanwhile, a cluster line-card device, a cluster central exchange device, and a cluster system are further provided. In implementation, smooth expansion can be achieved without interrupting running equipment services in the CLC current network and without interrupting data services. Moreover, during the expansion process, hardware equipment needs not to be replaced, thus investment of users on the equipment is reduced. | 08-25-2011 |
20140380434 | METHOD AND TRUSTED GATEWAY FOR WIFI TERMINAL ACCESSING TO PACKET DATA PS SERVICE DOMAIN - The embodiments of the present invention provide a method and a trusted gateway for a WiFi terminal to access a PS service domain. The method comprises: receiving an accounting request message sent by an authentication, authorization and accounting AAA server or a dynamic host configuration protocol DHCP request message sent by the WiFi terminal; establishing, by a trusted gateway, a first packet data protocol PDP context connection or a first packet data network PDN connection with the PS service domain according to attribute information of the WiFi terminal after receiving the accounting request message or the DHCP request message, so that the WiFi terminal accesses the PS service domain via the wireless local area network, the trusted gateway, and the established first PDP context connection or the first PDN connection. | 12-25-2014 |
20150042315 | BIOELECTRIC SIGNAL DETECTING CIRCUITS, LEAD WIRE DETECTING CIRCUITS AND MEDICAL DEVICES - This disclosure relates to bioelectric signal detecting circuits, lead wire detecting circuits and medical devices. The lead wire detecting circuit may include a reference voltage generator, at least one comparator, and a logic control module, wherein input ends of the comparator are connected to an output end of the reference voltage generator and an signal output end of a lead wire, respectively, for inputting a reference voltage and a lead signal, and the comparator compares the lead signal with the reference voltage and changes an output voltage at an output end of the comparator according to a comparison result; wherein an input end of the logic control module is connected to the output end of the comparator, and the logic control module determines whether the lead wire is in a connected state or disconnected state by the output voltage at the output end of the comparator. | 02-12-2015 |
Patent application number | Description | Published |
20120020169 | TWO-PORT SRAM WRITE TRACKING SCHEME - A Static Random Access Memory (SRAM) includes at least two memory cells sharing a read bit line (RBL) and a write bit line (WBL). Each memory cell is coupled to a respective read word line (RWL) and a respective write word line (WWL). A write tracking control circuit is coupled to the memory cells for determining a write time of the memory cells. The write tracking control circuit is capable of receiving an input voltage and providing an output voltage. The respective RWL and the respective WWL of each memory cell are asserted during a write tracking operation. | 01-26-2012 |
20120134219 | MODE CHANGING CIRCUITRY - A circuit includes a memory cell having a ground reference node, a switch coupled to the ground reference node, and a mode changing circuit having an output coupled to the switch. The mode changing circuit is configured to change a logic state of the output between a first output logic state and a second output logic state in response to a change in an operational voltage and/or temperature, thereby set the memory cell in a first mode in which the ground reference node is at first reference level or in a second mode in which the ground reference node is at a second reference level different from the first reference level. | 05-31-2012 |
20120206986 | AMPLIFIER SENSING - A circuit comprises a first read bit line, a second read bit line, and a sense amplifier. First and second read bit lines couple a plurality of memory cells and a reference cell of a memory array, respectively. The sense amplifier is configured to receive the first read bit line as a first input and the second read bit line as a second input. When a memory cell of the first plurality of memory cells is read, the memory cell is read activated, the first reference cell is configured to be off, the second reference cell is configured to be on, and the sense amplifier is configured to provide an output reflecting a data logic stored in the memory cell based on a voltage difference between a first voltage of the first read bit line and a second voltage of the second read bit line. | 08-16-2012 |
20130088927 | SYSTEM AND METHOD FOR GENERATING A CLOCK - A first clock is received by a memory macro. In response to a first clock transition of the first clock, a first transition of a second clock and of a third clock is generated. A tracking transition of a tracking signal is caused by the second clock. Based on a later transition of a second clock transition of the first clock and the tracking transition of the tracking signal, a second transition of the third clock is generated. The third clock is for use by an input-output of the memory macro. | 04-11-2013 |
20130094309 | TRACKING BIT CELL - A memory macro includes a tracking circuit and a plurality of memory cells. The tracking circuit has tracking transistors configured to receive a tracking voltage value. Each memory cell of the plurality of memory cells has memory transistors configured to receive a cell voltage value different from the tracking voltage value. The tracking circuit is configured to generate a tracking signal based on which a reading signal of a memory cell of the plurality of memory cells is generated. | 04-18-2013 |
20130208554 | TRACKING MECHANISMS - A tracking circuit in a memory macro includes a data line, a first tracking cell, and a plurality of transistors. The first tracking cell is electrically coupled to the data line. The plurality of transistors is electrically coupled to the data line. The plurality of transistors is configured to cause a delay on a transition of a signal of the data line based on a delay current. The signal of the data line is configured for use in generating a signal of a control line of a memory cell of the memory macro. | 08-15-2013 |
20130215693 | TRACKING CAPACITIVE LOADS - A time delay is determined to cover a timing of a memory cell in a memory macro having a tracking circuit. Based on the time delay, a capacitance corresponding to the time delay is determined. A capacitor having the determined capacitance is utilized. The capacitor is coupled to a first data line of a tracking cell of the tracking circuit. A first transition of the first data line causes a first transition of a second data line of the memory cell. | 08-22-2013 |
20130242678 | SIGNAL TRACKING IN WRITE OPERATIONS OF MEMORY CELLS - In a method, a first edge of a first tracking signal in a first direction of a memory array is generated. A first edge of a second tracking signal in a second direction of the memory array is generated. A first edge of a write-timing control signal is generated based on a slower edge of the first edge the first tracking signal and of the first edge of the second tracking signal. The first edge of the write-timing control signal is used to generate a second edge of the second tracking signal. | 09-19-2013 |
20130286761 | SWITCHING CIRCUIT - A first transistor is turned on based on a first control signal provided to a first terminal of the first transistor. A second transistor is turned on based on a second control signal delayed by a time delay from the first control signal. A second terminal of the first transistor is coupled with a second terminal of the second transistor. The second control signal is used to control a first input signal of a logic device. The logic device receives a second input signal inversed from the first control signal. An output signal of the logic device is used to control a first terminal of the second transistor. | 10-31-2013 |
20140032871 | TRACKING MECHANISM FOR WRITING TO A MEMORY CELL - A circuit includes a tracking write circuit and a write circuit. Various write signals of the write circuit are generated based on tracking signals of the tracking write circuit. The write signals are used in a write operation of a memory cell. | 01-30-2014 |
20140085993 | MULTIPLE BITCELLS TRACKING SCHEME SEMICONDUCTOR MEMORY ARRAY - A read tracking system and method for advanced memory devices are provided. The read tracking system and method include tracking multiple tracking bit cells in multiple segments and columns to incorporate device performance variation of bit cells in the memory array. The tracking path mimics the worst-case read path with some built-in margins to sufficiently and efficiently cover the read times of bit cells in a memory array without unnecessarily sacrificing the read speed performance of the memory array. A number of tracking cells may be placed at different segments and both sides of the memory array to cover read time variation across memory array. | 03-27-2014 |
20140092675 | TWO-PORT SRAM WRITE TRACKING SCHEME - A write tracking control circuit includes an input node, and a first transistor configured to pre-charge a word bit line connected to at least two memory cells. The write tracking control circuit further includes a second transistor configured to pre-charge a read bit line connected to the at least two memory cells. The write tracking control circuit further includes a first delay circuit between the input node and the first transistor, the first delay circuit configured to introduce a first delay time, wherein a gate of the first transistor is connected to the first delay circuit. The write tracking control circuit further includes a second delay circuit between the input node and the second transistor, the second delay circuit configured to introduce a second delay time different from the first delay time, wherein a gate of the second transistor is connected to the second delay circuit. | 04-03-2014 |
20140247675 | MULTIPLE BITCELLS TRACKING SCHEME SEMICONDUCTOR MEMORY ARRAY - A memory array includes a memory segment having at least one memory bank. The at least one memory bank includes an array of memory cells, and wherein at least two first read tracking cells are disposed in a read tracking column of the at least one memory bank. The memory array further includes a read tracking circuit coupled to the at least two first read tracking cells. Outputs of the at least two first read tracking cells are connected to a tracking bit connection line (TBCL). A tracking circuit connected to the TBCL is configured to output a tracking-cells output signal to generate a global tracking result signal to a memory control circuitry. The memory control circuitry is configured to reset a memory clock based on the global tracking result signal. | 09-04-2014 |
20140254289 | DATA CIRCUIT - A circuit includes a first plurality of memory cells coupled with a first data line and a first data transfer circuit coupled with the first data line and a second data line. In a first operation mode of the circuit, the first data line is left floating and is caused to have a first logical value by a current in at least one memory cell of the first plurality of memory cells. In a second operation mode of the circuit, the first data line is configured to reflect data stored in a memory cell of the plurality of memory cells, and the second data line is configured to reflect the data on the first data line through the first data transfer circuit. | 09-11-2014 |
20140268977 | ELECTRICAL LINES WITH COUPLING EFFECTS - A circuit includes a first line, a second line, a first sub-circuit, and a second sub-circuit. The first line has a first signal. The second line has a second signal. The first sub-circuit is configured to generate a first output signal. The second sub-circuit is configured to generate a second output signal. The first output signal and the second output signal have coupling effects if the first signal and the second signal have coupling effects based on the first line and the second line. The first output signal and the second output signal do not have coupling effects if the first signal and the second signal do not have coupling effects. | 09-18-2014 |
20150029797 | MEMORY MACRO WITH A VOLTAGE KEEPER - A memory macro comprises a data line, a first interface circuit comprising a first node coupled to the data line, and a voltage keeper configured to control a voltage level at the first node, and a second interface circuit comprising a second node coupled with the data line, wherein the voltage keeper is configured to control a voltage level at the second node via the data line. | 01-29-2015 |
20150078105 | MODE CHANGING CIRCUITRY - A circuit includes a PMOS transistor, an NMOS transistor, and a logic level generation section comprising an input and a logic level output. The PMOS gate receives an input voltage having a voltage level determined based on an operational voltage, the PMOS drain is coupled to the NMOS drain and the input of the logic level generation section, and the PMOS source is coupled to the operational voltage. The NMOS gate receives a voltage that causes the NMOS transistor to have a first driving capability. The first driving capability of the NMOS transistor is less than that of the PMOS transistor if the input voltage has a voltage level greater than a predetermined voltage level. | 03-19-2015 |
20150098280 | TRACKING BIT CELL - A method includes determining a plurality of first current values of a first current to be sunk by a tracking cell of a tracking circuit in response to a plurality of first voltage values of a first voltage applied to the tracking cell. Each first current value of the plurality of first current values thereby corresponds to a first voltage value of the plurality of first voltage values. A second current value of a second current is determined. The second current value corresponds to a second voltage value of a second voltage of a memory cell of a plurality of memory cells. A third voltage value is selected based on the second current value, a first current value of the plurality of first current values, and a first voltage value corresponding to the first current value. | 04-09-2015 |
20150124548 | SWITCHING CIRCUIT - A first transistor is turned on based on a first control signal provided to a first terminal of the first transistor. A second control signal is generated by a logic device based on a first input signal and a second input signal. The first input signal is controlled by a logical value stored by a keeper circuit and based on the first control signal, and the second input signal is generated by inverting the first control signal. A second transistor is turned on based on the second control signal provided to a first terminal of the second transistor. A second terminal of the first transistor is coupled with a second terminal of the second transistor. | 05-07-2015 |
20150131391 | TRACKING MECHANISM FOR WRITING TO A MEMORY CELL - A circuit includes a write driver, a data circuit, a memory cell, a tracking write buffer, a tracking write driver, and a tracking cell. The circuit is configured that, during a write operation of the memory cell based on a clock signal, the write driver circuit is configured to generate a write control signal to control the memory cell; the data circuit is configured to provide write data to the memory cell; the tracking write buffer is configured to generate a tracking write control signal; and the tracking write driver is configured to generate a tracking write data signal to be transferred to the tracking cell. The tracking cell is configured to adjust a signal at a first node of the tracking cell based on a logical value of the tracking write data signal in response to the tracking write control signal. | 05-14-2015 |
20150162060 | MEMORY MACRO WITH A VOLTAGE KEEPER - A memory macro includes a first data line, a second data line, a first switch and a voltage keeper. The first switch is configured between the first data line and the second data line. The voltage keeper is electrically coupled to the second data line. The voltage keeper is configured to control a voltage level at the second data line in response to the voltage level at the second data line during the first switch electrically couples the second data line to the first data line. | 06-11-2015 |
20150162076 | DATA CIRCUIT - A circuit includes a first data line, a first plurality of memory cells coupled with the first data line, and a data transfer circuit coupled with the first data line. The data transfer circuit includes an output logic gate. The data transfer circuit is configured to, in a first operation mode in which the first plurality of memory cells is in a standby mode, set an output node of the output logic gate to be free from electrically coupled with a reference voltage and a supply voltage through the output logic gate. The data transfer circuit is configured to, in a second operation mode in which a memory cell of the first plurality of memory cells is selected to be read, set the output node of the output logic gate to be either electrically coupled with the reference voltage or with the supply voltage through the output logic gate. | 06-11-2015 |
20150213857 | TRACKING MECHANISMS - A tracking circuit in a memory macro includes a data line, a tracking cell electrically coupled with the data line, a logical gate, a feedback transistor, and a plurality of pulling devices. The logical gate has an input terminal and an output terminal. The input terminal of the logical gate is electrically coupled with the data line. The feedback transistor has a first terminal, a second terminal, and a gate terminal. The first terminal of the feedback transistor is electrically coupled with the data line, and the gate terminal of the feedback transistor is electrically coupled with the output terminal of the logical gate. The plurality of pulling devices is configured to pull the second terminal of the feedback transistor toward a first voltage. | 07-30-2015 |
20150213880 | WRITING DATA TO A MEMORY CELL - A circuit comprises a first transistor, a capacitive component, a second transistor, and a data line. The first transistor has a threshold voltage value. A first terminal of the first transistor is coupled with a first terminal of the capacitive component and a second terminal of the second transistor. A second terminal of the first transistor is configured to receive a second-terminal voltage value. A third terminal of the first transistor is configured to receive a third-terminal voltage value. A first terminal of the second transistor is coupled with the data line. A third terminal of the second transistor is configured to receive a second-transistor control signal. The first transistor is configured to be on and off to maintain the data line at a data line voltage value. | 07-30-2015 |
20150325287 | MEMORY ARRAY AND METHOD OF OPERATING THE SAME - A memory array includes an array of memory cells. The memory array further includes at least two read tracking cells in a read tracking column. The memory array further includes a read tracking circuit coupled to the at least two read tracking cells, wherein the read tracking circuit is configured to generate a global tracking result signal based on outputs from the at least two read tracking cells. The memory array further includes memory control circuitry, wherein the memory control circuitry is configured to reset a memory clock based on the global tracking result signal. | 11-12-2015 |
20150340085 | TRACKING BIT CELL AND METHOD - A method includes generating a first edge of a first tracking signal for a tracking cell, generating a first edge of a second tracking signal for the tracking cell based on the first edge of the first tracking signal, generating a first edge of a cell signal for a memory cell, generating a second edge of the first tracking signal based on the first edge of the second tracking signal, and generating a second edge of the cell signal based on the second edge of the first tracking signal. A transistor in the tracking cell operates at a tracking voltage value and a transistor in the memory cell operates at a memory voltage value different from the tracking voltage value. | 11-26-2015 |
20150348597 | CIRCUIT, METHOD OF USING THE CIRCUIT AND MEMORY MACRO INCLUDING THE CIRCUIT - A circuit includes a first latch for generating a first latched signal; and a first comparator for comparing the first latched signal and a write address, and generating a first comparator signal. The circuit includes a first logic circuit for receiving the first comparator signal and a fourth latched signal, and generating a first logic circuit output signal; and a second latch for receiving the first logic circuit output signal and generating a second latched signal. The circuit includes a third latch for generating a third latched signal; and a second comparator for comparing the third latched signal and a read address, and generating a second comparator signal. The circuit includes a second logic circuit for receiving the second comparator signal and the second latched signal, and generating a second logic circuit signal; and a fourth latch for receiving the second logic circuit signal and generating the fourth latched signal. | 12-03-2015 |
20160126941 | SWITCHING CIRCUIT - A circuit has an operational voltage supply node that carries an operational voltage having an operational voltage value, a reference voltage supply node that carries a reference voltage having a reference voltage value, and a sub-circuit and switching circuit between the operational voltage supply node and the reference voltage supply node. The switching circuit is in series with the sub-circuit and controls a current through the sub-circuit based on a difference between the operational voltage value and a nominal operational voltage value. | 05-05-2016 |
20160133316 | TRACKING CELL AND METHOD - A circuit includes a first power node that receives a first operational voltage having a first operational voltage level and a second power node that receives a second operational voltage having a second operational voltage level different from the first operational voltage level. A memory cell is coupled with the first power node, the memory cell configured to store a logic value, and a tracking cell is coupled with the second power node, the tracking cell configured to generate a signal having a timing responsive to the second operational voltage level. The circuit is configured to read the logic value of the memory cell based on the signal. | 05-12-2016 |
Patent application number | Description | Published |
20120129780 | LACTOFERRIN AND BRAIN HEALTH AND PROTECTION IN ADULTS - The present invention relates generally to the field of brain health, brain protection, maintenance of cognitive function, prevention of cognitive decline and cognitive disorders. Neuronal cells in the brain can be protected. Also cognitive performance can be increased. | 05-24-2012 |
20120171177 | NUTRITIONAL COMPOSITION FOR SUPPORTING BRAIN DEVELOPMENT AND FUNCTION OF TODDLERS - The present invention relates to a nutritional composition, in particular directed to toddlers and/or a weaning child, said nutritional composition comprising a protein source, a source of available carbohydrates, a lipid source, at least one probiotic microorganism, and prebiotics, wherein said lipid source comprises DHA (docosahexaenoic acid). The nutritional composition improves cognitive performance, in particular learning and memory of the child. Preferably, the composition comprises iron, zinc, vitamin D and/or sialic acid. Preferably, the composition comprises a source of phospholipids rich in DHA. | 07-05-2012 |
20120184483 | LACTOFERRIN AND NEURONAL HEALTH AND DEVELOPMENT IN THE INFANT GUT - The present invention relates generally to the field of neuronal health, neuronal protection and neuronal development. One embodiment of the present invention relates to a composition that can be used for the treatment or prevention of a delayed development of the enteric nervous system. Neuronal cells in the gut can be protected. Disorders linked to a delayed development of the enteric nervous system and/or to an impaired enteric nervous system can be treated or prevented by the administration of lactoferhn containing compositions. | 07-19-2012 |
20120184484 | LACTOFERRIN AND BRAIN HEALTH AND DEVELOPMENT IN INFANTS - The present invention relates generally to the field of brain development and brain health. One embodiment of the present invention relates to a composition that can be used for the treatment or prevention of a delayed brain development and/or a delayed development of the nervous system. Also cognitive performance can be increased. | 07-19-2012 |
20120270777 | LACTOFERRIN AND GUT NEURONAL HEALTH IN ADULTS AND/OR ELDERLY - The present invention relates generally to the field of neuronal health and neuronal protection. One embodiment of the present invention relates to a composition that can be used for the protection of the enteric nervous system from neurodegeneration. Disorders linked to an impaired enteric nervous system can be treated or prevented by the administration of lactoferrin containing compositions according to the present invention. | 10-25-2012 |
20140135262 | LACTOFERRIN AND GUT NEURONAL HEALTH IN ADULTS AND/OR ELDERLY - The present invention relates generally to the field of neuronal health and neuronal protection. One embodiment of the present invention relates to a composition that can be used for the protection of the enteric nervous system from neurodegeneration. Disorders linked to an impaired enteric nervous system can be treated or prevented by the administration of lactoferrin containing compositions according to the present invention. | 05-15-2014 |
20140288004 | LACTOFERRIN AND THE WHITE MATTER - The present invention generally relates to white matter. In particular, the present invention relates to a composition that can be used for promotion the development and/or void loss of white matter. One embodiment of the present invention relates to a composition comprising lactoferrin for use in the promotion of the development of the white matter, in the treatment or prevention of a delayed development of the white matter, and or in the treatment of prevention of a loss of white matter. | 09-25-2014 |
20150309092 | Current Pattern Matching Method for Non-Intrusive Power Load Monitoring and Disaggregation - A harmonic-characteristics based current pattern matching method for the non-intrusive power load monitoring and disaggregation is provided in this present invention, on the basis of establishing the load signature database, which comprises electrical appliance registration and load state word space initialization, data acquisition and data preprocessing, feasible state word space search based on table looking-up, the optimal matching of current pattern, and display and output of the monitoring and disaggregation results. The method improves the accuracy of disaggregation, and can achieves exact identification of operating states of appliances, and also can reduce the cost. | 10-29-2015 |
Patent application number | Description | Published |
20120174307 | SUCTION DEVICE FOR ENHANCING THE NEGATIVE PRESSURE OF THE SIPHON OF THE TOILET AND THE METHOD THEREOF - A method of enhancing the negative pressure of siphon of toilet is to suck the air between the two traps to enhance the negative pressure between the two seal-water, so as to rapidly form a siphon in the traps and flush the waste out rapidly. A suction device for enhancing the negative pressure of siphon of a toilet is used. It comprises: a water container installed in the water tank, said water container is provided with a water inlet and outlet; an air container with an opening in the bottom installed inside the water container, the lower portion of the side wall of the air container has a water opening connected to the water container; and a connecting tube, the bottom of which is connected to the trapway of the toilet, and the top is connected to the top of the air container. | 07-12-2012 |
20120240322 | AUXILIARY SIPHON DEVICE FOR THE TOILET - An auxiliary siphon device for the toilet has: a hollow air container, which is bottom-opened, an abdicating groove in which a drain valve can be installed in is vertically disposed in the sidewall of the air container, said abdicating groove is communicated with the water tank; through holes for water flow are provided in the sidewall of the air container in the lower portion of the abdicating groove; a sealing bottom cover communicated with the bottom of the air container, and a drain valve installing hole is disposed in the sealing bottom cover corresponding to bottom of the abdicating groove; and a connecting tube, the bottom end of which is connected to the trapway of the toilet, and the top end of which is connected to the top of the inside of the air container. | 09-27-2012 |
20130161333 | DUAL-DRAINAGE SWITCHING MECHANISM OF WATER TANK - A dual-drainage switching mechanism of water tank has: a water container with bottom opening of the inner cavity, an air vent communicating with the inner cavity is arranged on the sealed top; a valve unit used for controlling opens or closes of the air vent; a drain valve controller comprising a partial flush button and a full flush button, and he air vent is opened through the linking and coupling of the full flush button and the valve unit, and the air vent is closed through the linking and coupling of the partial flush button and the valve unit. The dual-draining switch is achieved through hermetically storing or non-hermetically controlling part of water body in the inner cavity of the water container, traditional one-pressing drain valve can be transformed into the draining control mechanism with dual-draining function. | 06-27-2013 |
20130199315 | LEVER CONTROL MECHANISM OF A DRAIN VALVE OF A TOILET TANK - A lever control mechanism of a drain valve of a toilet tank has a lever assembly assembled in the wall of the toilet tank and a lever linked to the revolving shaft of the lever assembly. The lever assembly is connected to a deviator, which is disposed with a drive arm; the drive arm is connected to the revolving shaft. The deviator is disposed with a joint portion and at least a leading hole to limit the lever revolving vertically. One end of the lever is run through the leading hole to rotationally connect to the joint portion; the drive arm is revolved by the driving of the revolving shaft to drive the lever revolved in the fan shaped vertical surface limited formed by the joint portion and the leading hole. | 08-08-2013 |
20130333104 | QUICK ASSEMBLY AND DISASSEMBLY MECHANISM WITH BUTTON LOCK FOR A TOILET COVER - A quick assembly and disassembly mechanism with a button lock for a toilet cover has a straight tube pivot joint, two stands and two pivot shafts. Each pivot shaft is disposed with pin holes in the radial direction. A lock bar disposed between the pivot shafts can slide side to side. The straight tube is disposed with an operation mechanism to drive the lock bar to slide. A spring is disposed inside the straight tube to reposition the lock bar. The lock bar is disposed with a lock catch and a lock piece with lock hole. The lock catch has an elastic body and a lock piece to limit the sliding of the lock bar and a pivot shaft, which is plugged to the end of the lock bar in sliding way. The lock piece in the end of the lock bar is disposed with a lock hole. | 12-19-2013 |
20140124047 | HEIGHT ADJUSTING MECHANISM FOR AN INLET VALVE - A height adjusting mechanism for an inlet valve includes a valve body, and inlet pipe, a retaining member and an actuator. The inlet pipe is sleeved in the valve body and connected to the valve body; the retaining member is assembled in the valve body; and the actuator can drive the retaining member to move to make the valve body fixed to the inlet pipe or moved relatively to the inlet pipe in the axial direction. The actuator drives the retaining member to move in order to let the valve body and the inlet pipe to be fixed or moved relatively to each other in the axial direction. There is no need to rotate the valve body during adjusting process, and the float won't affect the tank wall when the water valve body is rotating. | 05-08-2014 |
20140216583 | WATER DRAIN ACCELERATING DEVICE - A water drain accelerating device has a base with a discharge port connected to a flush way assembled inside a water tank. An overflow hole is connected to the discharge port. An overflow pipe is plugged to the base. The bottom of the overflow pipe is connected to the overflow hole. A negative pressure pipe is connected to the overflow pipe. Negative pressure generates inside the overflow pipe when the base is draining. Water inside the water tank flows out of the discharge port when water drains. The water level inside the cavity of the negative pressure pipe falls down with the water level inside the water tank. Negative pressure generates inside the overflow pipe, so air inside the overflow pipe can't enter into the discharge port through the overflow hole. An air pipe extends from the overflow hole to the flush way. | 08-07-2014 |