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Bing Dang
Bing Dang, Yorktown Heights, NY US
| Patent application number | Description | Published |
|---|---|---|
| 20110044369 | SILICON CARRIER OPTOELECTRONIC PACKAGING - An optoelectronic (OE) package or system and method for fabrication is disclosed which includes a silicon layer with wiring. The silicon layer has an optical via for allowing light to pass therethrough. An optical coupling layer is bonded to the silicon layer, and the optical coupling layer includes a plurality of microlenses for focusing and or collimating the light through the optical via. A plurality of OE elements are coupled to the silicon layer and electrically communicating with the wiring. At least one of the OE elements positioned in optical alignment with the optical via for receiving the light. A carrier is interposed between electrical interconnect elements. The carrier is positioned between the wiring of the silicon layer and a circuit board and the carrier is electrically connecting first interconnect elements connected to the wiring of the silicon layer and second interconnect elements connected to the circuit board. | 02-24-2011 |
Bing Dang, Chappaqua, NY US
| Patent application number | Description | Published |
|---|---|---|
| 20080206960 | REWORKABLE CHIP STACK - A method for removing a thinned silicon structure from a substrate, the method includes selecting the silicon structure with soldered connections for removal; applying a silicon structure removal device to the silicon structure and the substrate, wherein the silicon structure removal device comprises a pre-determined temperature setpoint for actuation within a range from about eighty percent of a melting point of the soldered connections to about the melting point; heating the silicon structure removal device and the soldered connections of the silicon structure to within the range to actuate the silicon structure removal device; and removing the thinned silicon structure. Also disclosed is a structure including a plurality of layers, at least one layer including a thinned silicon structure and solder coupling the layer to another layer of the plurality; wherein the solder for each layer has a predetermined melting point. | 08-28-2008 |
| 20090072392 | Techniques For Forming Solder Bump Interconnects - Interconnects are formed on attachment points of a wafer by performing several steps. A plurality of cavities having a predetermined shape is formed in a semiconductor substrate. These cavities are then filled with an interconnect material to form the interconnects. The interconnects are subsequently attached to the attachment points of the wafer. | 03-19-2009 |
| 20090085202 | Methods and Apparatus for Assembling Integrated Circuit Device Utilizing a Thin Si Interposer - Methods of assembling an integrated circuit are provided. An interposer supported by an integrated handler is solder bumped onto one or more bond pads on a substrate. The integrated handler is removed from the interposer. A side of the interposer opposite that of the substrate is solder bumped to one or more bond pads on a chip. | 04-02-2009 |
| 20090311849 | METHODS OF SEPARATING INTEGRATED CIRCUIT CHIPS FABRICATED ON A WAFER - Improved methods of separating integrated circuit chips fabricated on a single wafer are provided. In an embodiment, a method of separating integrated circuit chips fabricated on a wafer comprises: attaching a support to a back surface of the wafer; dicing the wafer to form individual integrated circuit chips attached to the support; attaching a carrier comprising a releasable adhesive material to a front surface of the wafer opposite from the back surface; separating the support from the back surface of the wafer; subjecting the carrier to an effective amount of heat, radiation, or both to reduce the adhesiveness of the adhesive material to allow for removal of at least one of the integrated circuit chips from the carrier; and picking up and moving at least one of the integrated circuit chips using a tool configured to handle the integrated circuit chips. | 12-17-2009 |
| 20100326702 | INTEGRATED CIRCUIT ASSEMBLY - Methods and apparatus for forming an integrated circuit assembly are presented, for example, three dimensional integrated circuit assemblies. Lower height 3DIC assemblies due Use of, for example, thinned wafers, low-height solder bumps, and through silicon vias provide for low height three dimensional integrated circuit assemblies. For example, a method for forming an integrated circuit assembly comprises forming first solder bumps on a first die, and forming a first structure comprising the first die, the first solder bumps, a first flux, and a first substratum. The first die is placed upon the first substratum. The first solder bumps are between the first die and the first substratum. The first flux holds the first die substantially flat and onto the first substratum. | 12-30-2010 |
Bing Dang, Ossining, NY US
| Patent application number | Description | Published |
|---|---|---|
| 20090194864 | INTEGRATED MODULE FOR DATA PROCESSING SYSTEM - An apparatus for an integrated module. A silicon carrier with through-silicon vias has a plurality of die connected to a top side of the silicon carrier. In addition, a substrate is connected to a bottom side of the silicon carrier. The substrate is coupled to the plurality of die via the through-silicon vias. | 08-06-2009 |
| 20090298236 | Integrated Module for Data Processing System - An apparatus for an integrated module. A silicon carrier with through-silicon vias has a plurality of die connected to a top side of the silicon carrier. In addition, a substrate is connected to a bottom side of the silicon carrier. The substrate is coupled to the plurality of die via the through-silicon vias. | 12-03-2009 |
| 20100086739 | MICROCAVITY STRUCTURE AND PROCESS - A microcavity structure is provided. The structure comprises a cavity layout that enables centering of reflowed solder at each of one or more interconnect locations and protrusion of the reflowed solder sufficiently from the cavity to facilitate wetting. Techniques are also provided for producing a microcavity structure, for using injection molded solder (IMS) for micro bumping, as well as for using injection molded solder (IMS) for three-dimensional (3D) packaging. | 04-08-2010 |
Bing Dang, Atlanta, GA US
| Patent application number | Description | Published |
|---|---|---|
| 20090294954 | 3-D ICs WITH MICROFLUIDIC INTERCONNECTS AND METHODS OF CONSTRUCTING SAME - Three dimensional integrated circuits with microfluidic interconnects and methods of constructing same are provided. According to some embodiments, and microfluidic integrated circuit system can comprise a plurality of semiconductor die wafers each having a top and bottom exterior surface. The semiconductor die wafers can form a stack of die wafers. The die wafers can comprise one or more channels formed through the die wafers. The channels can extend generally between top and bottom exterior surfaces of the semiconductor die wafers. A plurality of micro-pipes can be disposed between adjacent semiconductor die wafers in the stack. The micro-pipes can enable the channels to be in fluid communication with each other. A barrier layer can be disposed within at least one of the channels and the micro-pipes. The barrier layer can be adapted to prevent a coolant flowing through the at least one of the channels and the micro-pipes from leeching into the channels and micro-pipes. Other embodiments are also claimed and described. | 12-03-2009 |