| Patent application number | Description | Published |
|---|
| 20080270064 | M1 Testable Addressable Array for Device Parameter Characterization - An integrated circuit device and device parameter characterization method are provided. The integrated circuit device has a padset with plurality of pads. The integrated circuit device also includes one or more arrays of devices under test, each of the one or more arrays disposed between two of the plurality of pads. The integrated circuit device further includes one or more n-bit decoders, each disposed between two of the plurality of pads and electrically coupled to a corresponding one of the one or more arrays. Each n-bit decoder comprises one or more outputs that deliver a defined voltage to each device under test in the corresponding one of the one or more arrays of devices under test. The integrated circuit device and corresponding electrical connections are implemented in a single level of metal. | 10-30-2008 |
| 20090271134 | Methods and Apparatus for Determining a Switching History Time Constant in an Integrated Circuit Device - Techniques for inline measurement of a switching history time constant in an integrated circuit device are provided. A series of pulses is launched into a first stage of a delay chain comprising a plurality of delay stages connected in series and having a length greater than a decay length of at least an initial one of the series of pulses, such that the at least initial one of the series of pulses does not appear at a second stage of the delay chain. An amount of time between the launching of the initial one of the series of pulses and the appearance of at least one of the series of pulses at the second stage of the delay chain is determined. The switching history time constant is calculated as a function of a number of stages traversed by the at least one pulse, the determined amount of time, and the decay length of the at least initial one of the series of pulses based at least in part on a switching history of the integrated circuit device. | 10-29-2009 |
| 20110043215 | SINGLE LEVEL OF METAL TEST STRUCTURE FOR DIFFERENTIAL TIMING AND VARIABILITY MEASUREMENTS OF INTEGRATED CIRCUITS - A test structure for an integrated circuit device includes one or more experiments selectively configured to receive one or more high-speed input signals as inputs thereto and to output at least one high-speed output signal therefrom, the one or more experiments each comprising two or more logic gates configured to determine differential delay characteristics of individual circuit devices, at a precision level on the order of picoseconds to less than 1 picosecond; and wherein the one or more sets of experiments are disposed, and are fully testable, at a first level of metal wiring (M | 02-24-2011 |
| 20110043242 | ACQUISITION OF SILICON-ON-INSULATOR SWITCHING HISTORY EFFECTS STATISTICS - A test structure for gathering switching history effect statistics includes a waveform generator circuit that selectively generates a first test waveform representative of a 1SW transistor switching event, and a second test waveform representative of a 2SW transistor switching event; and a history element circuit coupled to the waveform generator circuit, the history element circuit including a device under test (DUT) therein, and a variable delay chain therein, wherein a selected one of the first and second test waveforms are input to the DUT and the variable delay chain; wherein the history element circuit determines fractional a change in signal propagation delay through the DUT between the 1SW and 2SW transistor switching events, with the fractional change in signal propagation delay calibrated with timing measurements of a variable frequency ring oscillator; and wherein the test structure utilizes only external low-speed input and output signals with respect to a chip. | 02-24-2011 |
| 20110043243 | MEASUREMENT OF PARTIALLY DEPLETED SILICON-ON-INSULATOR CMOS CIRCUIT LEAKAGE CURRENT UNDER DIFFERENT STEADY STATE SWITCHING CONDITIONS - A test system for determining leakage of an integrated circuit (IC) under test includes a test circuit formed on a same chip as the IC, the test circuit further having pulse generator configured to generate a high-speed input signal to the IC at a plurality of selectively programmable duty cycles and frequencies, the IC powered from a first power source independent from a second power source that powers the pulse generator; and a current measuring device configured to measure leakage current through the IC in a quiescent state, and current through the IC in an active switching state, responsive to the high-speed input signal at a plurality of the programmable duty cycles and frequencies, and wherein the test circuit utilizes only external low-speed input and output signals with respect to the chip. | 02-24-2011 |
| 20110169499 | HIGH SPEED MEASUREMENT OF RANDOM VARIATION/YIELD IN INTEGRATED CIRCUIT DEVICE TESTING - A test structure is provided that utilizes a time division sampling technique along with a statistical modeling technique that uses metal-oxide-semiconductor field effect transistor (MOSFET) saturation and linear characteristics to measure the mean (average) and sigma (statistical characterization of the variation) of a large population of electrical characteristics of electrical devices (e.g., integrated circuits) at high speed. Such electrical characteristics or sampling parameters include drive currents, leakage, resistances, etc. | 07-14-2011 |
| Patent application number | Description | Published |
|---|
| 20100063152 | Method and Topical Formulation for Treating Localized Edema - Methods and formulations are provided for the treatment of localized edema, particularly localized edema resulting from chronic venous insufficiency. A metal ion sequestrant is topically administered to a subject afflicted with localized edema in combination with a permeation enhancer selected from methylsulfonylmethane and a combination of methylsulfonylmethane and dimethylsulfoxide. Topically administrable formulations for use in the aforementioned method are also provided. | 03-11-2010 |
| 20100069335 | Prevention and Treatment of Ophthalmic Complications of Diabetes - An method and formulation are provided for the prevention and treatment of adverse ocular conditions which are complications of diabetes. In one embodiment, the invention comprises administering to a person having diabetes, insulin resistance, or a risk factor for diabetes a formulation comprising a metal chelator and a transport enhancer. Most preferably, the metal chelator is EDTA or a salt of EDTA, and the transport enhancer is methylsulfonylmethane (MSM). The formulation may be in a form suitable for application to the eye itself, for example, in the form of eye drops. | 03-18-2010 |
| 20100209419 | Method and formulation for treating adverse biological conditions - A method for treatment of adverse biological conditions is provided, wherein a biologically active agent such as a macromolecular biomolecule, e.g., a nucleic acid or a peptidic compound, is administered to a subject in need of such treatment in a formulation containing a transport enhancer having the structure of formula (I) | 08-19-2010 |
