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Bhattacharyya, CA
Gautam Bhattacharyya, Fremont, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20100261354 | GASKET WITH POSITIONING FEATURE FOR CLAMPED MONOLITHIC SHOWERHEAD ELECTRODE - An electrode assembly for a plasma reaction chamber used in semiconductor substrate processing. The assembly includes an upper showerhead electrode which is mechanically attached to a backing plate by a series of spaced apart cam locks. A thermally and electrically conductive gasket with projections thereon is compressed between the showerhead electrode and the backing plate at a location three to four inches from the center of the showerhead electrode. A guard ring surrounds the backing plate and is movable to positions at which openings in the guard ring align with openings in the backing plate so that the cam locks can be rotated with a tool to release locking pins extending from the upper face of the electrode. | 10-14-2010 |
| 20110073257 | UNITIZED CONFINEMENT RING ARRANGEMENTS AND METHODS THEREOF - An arrangement for performing pressure control in a plasma processing chamber comprising an upper electrode, a lower electrode, a unitized confinement ring arrangement wherein the upper electrode, the lower electrode and the unitized confinement ring arrangement are configured at least for surrounding a confined chamber region to facilitate plasma generation and confinement therein. The arrangement further includes at least one plunger configured for moving the unitized confinement ring arrangement in a vertical direction to adjust at least one of a first gas conductance path and a second gas conductance path to perform the pressure control, wherein the first gas conductance path is formed between the upper electrode and the unitized confinement ring arrangement and the second gas conductance path is formed between the lower electrode and the single unitized ring arrangement. | 03-31-2011 |
Gautam Bhattacharyya, San Ramon, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20110070740 | CLAMPED MONOLITHIC SHOWERHEAD ELECTRODE - An electrode assembly for a plasma reaction chamber used in semiconductor substrate processing. The assembly includes an upper showerhead electrode which is mechanically attached to a backing plate by a series of spaced apart cam locks. A guard ring surrounds the backing plate and is movable to positions at which openings in the guard ring align with openings in the backing plate so that the cam locks can be rotated with a tool to release locking pins extending from the upper face of the showerhead electrode. | 03-24-2011 |
| 20110104884 | HOT EDGE RING WITH SLOPED UPPER SURFACE - A hot edge ring with extended lifetime comprises an annular body having a sloped upper surface. The hot edge ring includes a step underlying an outer edge of a semiconductor substrate supported in a plasma processing chamber wherein plasma is used to process the substrate. The step includes a vertical surface which surrounds the outer edge of the substrate and the sloped upper surface extends upwardly and outwardly from the upper periphery of the vertical surface. | 05-05-2011 |
Manoj K. Bhattacharyya, Palo Alto, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20110020036 | Liquid Electrophotographic Printer - The present disclosure is drawn to apparatuses, methods, and systems involving liquid electrophotographic printing. Generally, a liquid electrophotographic printer can comprise an ink application device that is configured to apply liquid electrophotographic ink to a substrate, and a roller having a tacky surface that removes excess material from the surface of the substrate thereby pretreating the substrate prior to receiving the liquid electrophotographic ink. | 01-27-2011 |
| 20110073134 | PROCESS FOR REMOVING INK FROM PRINTED SUBSTRATE - A process for removing ink from a printed media substrate. Such process includes the step of providing a media substrate including an ink printed image wherein the ink composition or the media substrate contains photolabile entities. Then the process includes the step of applying UV light on the printed substrate wherein the emitted UV light has a wavelength value which is below the threshold wavelength of the photolabile entities. | 03-31-2011 |
| 20110102003 | Method For Measuring Conductivity Of Ink - Methods and devices for measuring conductivity of ink in a printing system are disclosed. An embodiment of the method is used with a printing system comprising a developer roller, wherein the ink is formed on the developer roller using electrostatic forces. The method comprises printing on a substrate using the ink; measuring a first current that charges the developer roller during the printing; and determining the conductivity of the ink, wherein the conductivity is proportional to the square of the first current. | 05-05-2011 |
| 20110104409 | INKJET PRINT MEDIA - An inkjet print medium includes a base substrate, a layer of a deinking solution at least partially diffused into the base substrate, and an ink-receiving layer established on the layer of the deinking solution. The deinking solution includes a flocculant in an amount ranging from about 0.1 wt. % to about 40 wt. % of a total wt. % of the deinking solution. | 05-05-2011 |
| 20110104441 | COMPOSITE COATING AND SUBSTRATE USED IN LIQUID ELECTROPHOTOGRAPHIC PRINTING AND METHOD - A digital-printing substrate and method of improving adhesion of a substrate to an liquid electrophotographic (LEP) ink in LEP printing both employ a composite coating. The composite coating includes from 4.5% to 9.5% by weight of a mineral pigment and from 0.5% to 2% by weight of an organic binder uniformly dispersed in water. The mineral pigment has a particle size less than 1 micron. The organic binder comprises a hydroxylated polymer having an average molecular weight greater than 50,000. A weight percentage of hydroxyl groups in the hydroxylated polymer is equal to or greater than a weight percentage of acidic groups in an LEP ink. The composite coating enhances adhesion of the LEP ink to the substrate comprising the composite coating dried on a surface of the substrate. | 05-05-2011 |
Manoj K. Bhattacharyya, Los Altos, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20100239968 | POLYMER COATED TONER PIGMENTS FOR ELECTROPHOTOGRAPHIC PRINTING - Toner compositions for electrophotographic printing are disclosed, along with methods for making such toners, and printing systems utilizing them. The disclosed process imparts qualities to the toner making it more efficiently and effectively incorporated into printed images. | 09-23-2010 |
Manoj K. Bhattacharyya, Cupertino, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20080299680 | METHODS OF FORMING MAGNETIC MEMORY DEVICES - Methods for creating a memory device can include depositing a sense layer, patterning the sense layer to form a plurality of magnetic data cells, depositing a separation layer over the plurality of data cells, depositing a reference layer over the separation layer, and patterning the reference layer to form an elongated magnetic reference cell wherein the elongated magnetic reference cell extends uninterrupted along more than one of the plurality of magnetic data cells. | 12-04-2008 |
Manosiz Bhattacharyya, San Jose, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20100281004 | STORING COMPRESSION UNITS IN RELATIONAL TABLES - A database server stores compressed units in data blocks of a database. A table (or data from a plurality of rows thereof) is first compressed into a “compression unit” using any of a wide variety of compression techniques. The compression unit is then stored in one or more data block rows across one or more data blocks. As a result, a single data block row may comprise compressed data for a plurality of table rows, as encoded within the compression unit. Storage of compression units in data blocks maintains compatibility with existing data block-based databases, thus allowing the use of compression units in preexisting databases without modification to the underlying format of the database. The compression units may, for example, co-exist with uncompressed tables. Various techniques allow a database server to optimize access to data in the compression unit, so that the compression is virtually transparent to the user. | 11-04-2010 |
| 20100281079 | COMPRESSION ANALYZER - Techniques are described herein for automatically selecting the compression techniques to be used on tabular data. A compression analyzer gives users high-level control over the selection process without requiring the user to know details about the specific compression techniques that are available to the compression analyzer. Users are able to specify, for a given set of data, a “balance point” along the spectrum between “maximum performance” and “maximum compression”. The point thus selected is used by the compression analyzer in a variety of ways. For example, in one embodiment, the compression analyzer uses the user-specified balance point to determine which of the available compression techniques qualify as “candidate techniques” for the given set of data. The compression analyzer selects the compression technique to use on a set of data by actually testing the candidate compression techniques against samples from the set of data. After testing the candidate compression techniques against the samples, the resulting compression ratios are compared. The compression technique to use on the set of data is then selected based, in part, on the compression ratios achieved during the compression tests performed on the sample data. | 11-04-2010 |
Nupur Bhattacharyya, Mountain View, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20090125866 | METHOD FOR PERFORMING PATTERN DECOMPOSITION FOR A FULL CHIP DESIGN - A method for decomposing a target pattern containing features to be printed on a wafer into multiple patterns. The method includes the steps of segmenting the target pattern into a plurality of patches; identifying critical features within each patch which violate minimum spacing requirements; generating a critical group graph for each of the plurality of patches having critical features, where the critical group graph of a given patch defines a coloring scheme of the critical features within the given patch, and the critical group graph identifies critical features extending into adjacent patches to the given patch; generating a global critical group graph for the target pattern, where the global critical group graph includes the critical group graphs of each of the plurality of patches, and an identification of the features extending into adjacent patches; and coloring the target pattern based on the coloring scheme defined by the global critical group graph. | 05-14-2009 |
| 20090172630 | AUTOMATED PROCESSOR GENERATION SYSTEM AND METHOD FOR DESIGNING A CONFIGURABLE PROCESSOR - A system for generating processor hardware supports a language for significant extensions to the processor instruction set, where the designer specifies only the semantics of the new instructions and the system generates other logic. The extension language provides for the addition of processor state, including register files, and instructions that operate on that state. The language also provides for new data types to be added to the compiler to represent the state added. It allows separate specification of reference semantics and instruction implementation, and uses this to automate design verification. In addition, the system generates formatted instruction set documentation from the language specification. | 07-02-2009 |
| 20090177876 | AUTOMATED PROCESSOR GENERATION SYSTEM AND METHOD FOR DESIGNING A CONFIGURABLE PROCESSOR - A system for generating processor hardware supports a language for significant extensions to the processor instruction set, where the designer specifies only the semantics of the new instructions and the system generates other logic. The extension language provides for the addition of processor state, including register files, and instructions that operate on that state. The language also provides for new data types to be added to the compiler to represent the state added. It allows separate specification of reference semantics and instruction implementation, and uses this to automate design verification. In addition, the system generates formatted instruction set documentation from the language specification. | 07-09-2009 |
Santosh Bhattacharyya, San Jose, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20090041332 | METHODS FOR GENERATING A STANDARD REFERENCE DIE FOR USE IN A DIE TO STANDARD REFERENCE DIE INSPECTION AND METHODS FOR INSPECTING A WAFER - Methods for generating a standard reference die for use in a die to standard reference die inspection and methods for inspecting a wafer are provided. One computer-implemented method for generating a standard reference die for use in a die to standard reference die inspection includes acquiring output of an inspection system for a centrally located die on a wafer and one or more dies located on the wafer. The method also includes combining the output for the centrally located die and the one or more dies based on within die positions of the output. In addition, the method includes generating the standard reference die based on results of the combining step. | 02-12-2009 |
| 20090080759 | SYSTEMS AND METHODS FOR CREATING PERSISTENT DATA FOR A WAFER AND FOR USING PERSISTENT DATA FOR INSPECTION-RELATED FUNCTIONS - Various systems and methods for creating persistent data for a wafer and using persistent data for inspection-related functions are provided. One system includes a set of processor nodes coupled to a detector of an inspection system. Each of the processor nodes is configured to receive a portion of image data generated by the detector during scanning of a wafer. The system also includes an array of storage media separately coupled to each of the processor nodes. The processor nodes are configured to send all of the image data or a selected portion of the image data received by the processor nodes to the arrays of storage media such that all of the image data or the selected portion of the image data generated by the detector during the scanning of the wafer is stored in the arrays of the storage media. | 03-26-2009 |
| 20090287440 | SYSTEMS AND METHODS FOR DETECTING DEFECTS ON A WAFER AND GENERATING INSPECTION RESULTS FOR THE WAFER - Systems and methods for detecting defects on a wafer and generating inspection results for the wafer are provided. One method includes detecting defects on a wafer by comparing output generated by scanning of the wafer performed by an inspection system to one or more defect detection thresholds. The method also includes sampling outliers in the output by selecting the output having the highest values from bins defined based on one or more predetermined criteria. In addition, the method includes selecting a portion of the sampled outliers based on wafer-level analysis of the sampled outliers. The method further includes generating inspection results for the wafer by combining information about the selected portion of the sampled outliers with information about the defects detected using the one or more defect detection thresholds. | 11-19-2009 |
| 20100329540 | METHODS FOR GENERATING A STANDARD REFERENCE DIE FOR USE IN A DIE TO STANDARD REFERENCE DIE INSPECTION AND METHODS FOR INSPECTING A WAFER - Methods for generating a standard reference die for use in a die to standard reference die inspection and methods for inspecting a wafer are provided. One computer-implemented method for generating a standard reference die for use in a die to standard reference die inspection includes acquiring output of an inspection system for a centrally located die on a wafer and one or more dies located on the wafer. The method also includes combining the output for the centrally located die and the one or more dies based on within die positions of the output. In addition, the method includes generating the standard reference die based on results of the combining step. | 12-30-2010 |
Suchita Bhattacharyya, San Diego, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20100247554 | USE OF TAM RECEPTOR INHIBITORS AS ANTIMICROBIALS - This disclosure concerns antimicrobial compositions and methods for immunoenhancement, for example methods of increasing production of a type I interferon (IFN) in response to pathogen infection, by administration of a TAM receptor inhibitor. In certain embodiments, the disclosure concerns methods of using a TAM receptor inhibitor to treat a viral or bacterial infection in a subject. | 09-30-2010 |