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| 20090108336 | METHOD FOR ADJUSTING THE HEIGHT OF A GATE ELECTRODE IN A SEMICONDUCTOR DEVICE - By providing an implantation blocking material on the gate electrode structures of advanced semiconductor devices during high energy implantation processes, the required shielding effect with respect to the channel regions of the transistors may be accomplished. In a later manufacturing stage, the implantation blocking portion may be removed to reduce the gate electrode height to a desired level in order to enhance the process conditions during the deposition of an interlayer dielectric material, thereby significantly reducing the risk of creating irregularities, such as voids, in the interlayer dielectric material, even in densely packed device regions. | 04-30-2009 |
| 20090243049 | DOUBLE DEPOSITION OF A STRESS-INDUCING LAYER IN AN INTERLAYER DIELECTRIC WITH INTERMEDIATE STRESS RELAXATION IN A SEMICONDUCTOR DEVICE - Enhanced efficiency of a stress relaxation implantation process may be achieved by depositing a first layer of reduced thickness and relaxing the same at certain device regions, thereby obtaining an enhanced amount of substantially relaxed dielectric material in close proximity to the transistor under consideration, wherein a desired high amount of stressed dielectric material may be obtained above other transistors by performing a further deposition process. Hence, the negative effect of the highly stressed dielectric material for specific transistors, for instance in densely packed device regions, may be significantly reduced by depositing the highly stressed dielectric material in two steps with an intermediate relaxation implantation process. | 10-01-2009 |
| 20090273035 | METHOD FOR SELECTIVELY REMOVING A SPACER IN A DUAL STRESS LINER APPROACH - By integrating a spacer removal process into the sequence for patterning a first stress-inducing material during a dual stress liner approach, the sidewall spacer structure for one type of transistor may be maintained, without requiring additional lithography steps. | 11-05-2009 |
| 20090321850 | Threshold adjustment for MOS devices by adapting a spacer width prior to implantation - Different threshold voltages of transistors of the same conductivity type in a complex integrated circuit may be adjusted on the basis of different Miller capacitances, which may be accomplished by appropriately adapting a spacer width and/or performing a tilted extension implantation. Thus, efficient process strategies may be available to controllably adjust the Miller capacitance, thereby providing enhanced transistor performance of low threshold transistors while not unduly contributing to process complexity compared to conventional approaches in which threshold voltage values may be adjusted on the basis of complex halo and well doping regimes. | 12-31-2009 |
| 20100133628 | HIGH-K GATE ELECTRODE STRUCTURE FORMED AFTER TRANSISTOR FABRICATION BY USING A SPACER - During a replacement gate approach, the inverse tapering of the opening obtained after removal of the polysilicon material may be reduced by depositing a spacer layer and forming corresponding spacer elements on inner sidewalls of the opening. Consequently, the metal-containing gate electrode material and the high-k dielectric material may be deposited with enhanced reliability. | 06-03-2010 |
| 20100190309 | METHOD FOR ADJUSTING THE HEIGHT OF A GATE ELECTRODE IN A SEMICONDUCTOR DEVICE - By providing an implantation blocking material on the gate electrode structures of advanced semiconductor devices during high energy implantation processes, the required shielding effect with respect to the channel regions of the transistors may be accomplished. In a later manufacturing stage, the implantation blocking portion may be removed to reduce the gate electrode height to a desired level in order to enhance the process conditions during the deposition of an interlayer dielectric material, thereby significantly reducing the risk of creating irregularities, such as voids, in the interlayer dielectric material, even in densely packed device regions. | 07-29-2010 |
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| 20080199674 | Polyethylene Molding Composition for Producing Blown Films Having Improved Mechanical Properties and Processability - The invention relates to a polyethylene molding composition having a multimodal molar mass distribution particularly suitable for blow molding films having a thickness in the range from 8 to 200 μm. The molding composition has a density at a temperature of 23° C. in the range from 0.948 to 0.953 g/cm | 08-21-2008 |
| 20080274353 | Polyethylene Molding Composition for External Sheathing of Electric Cables - The invention relates to a polyethylene molding composition which has a multimodal molar mass distribution and is particularly suitable for producing external sheathing of electric or information transmission cables. The molding composition has a density at a temperature of 23° C. in the range from 0.94 to 0.95 g/cm | 11-06-2008 |
| 20090105422 | Multimodal polyethylene molding composition for producing pipes having improved mechanical properties - A polyethylene molding composition having a multimodal molecular mass distribution and comprising from 45 to 55% by weight of a low molecular weight ethylene homopolymer A, from 20 to 40% by weight of a high molecular weight copolymer B comprising ethylene and another olefin having from 4 to 8 carbon atoms and from 15 to 30% by weight of an ultrahigh molecular weight ethylene copolymer C can be prepared in the presence of a Ziegler catalyst in a three-stage process and is highly suitable for producing pipes having excellent mechanical properties. | 04-23-2009 |
| 20100010163 | Polyethylene Molding Composition for Producing Injection-Molded Finished Parts - The invention relates to a polyethylene molding composition which has a multimodal molecular mass distribution and comprises a low molecular weight ethylene homopolymer A, a high molecular weight ethylene copolymer B and an ultrahigh molecular weight ethylene copolymer C. The molding composition has a density at a temperature of 23° C. in the range from 0.940 to 0.957 g/cm | 01-14-2010 |
| 20100301054 | POLYETHYLENE MOLDING COMPOSITION FOR PRODUCING HOLLOW CONTAINERS BY THERMOFORMING AND FUEL CONTAINERS PRODUCED THEREWITH - The present invention relates to a polyethylene molding composition which has a multimodal molar mass distribution and is particularly suitable for thermoforming to produce fuel containers having a capacity in the range from 20 to 200 I. The molding composition has a density at a temperature of 23° C. in the range from 0.948 to 0.953 g/cm | 12-02-2010 |
| 20110045295 | ADHESIVE POLYMER COMPOSITION - A novel adhesive composition suitable for composing multilayered coatings onto large, industrial equipment such as pipeline tubes is devised. The composition is a blend based on a polyethylene which determines the blend's favorable properties, which polyethylene itself can be used further in coating cables and for producing mouldings, especially rotomoulded articles. | 02-24-2011 |
| 20110171450 | Process for preparing a blown film from a polyethylene molding composition - The invention relates to a polyethylene molding composition having a multimodal molar mass distribution particularly suitable for blow molding films having a thickness in the range from 8 to 200 μm. The molding composition has a density at a temperature of 23° C. in the range from 0.948 to 0.953 g/cm | 07-14-2011 |
| 20110172362 | Process for preparing a polyethylene molding composition - The invention relates to a polyethylene molding composition having a multimodal molar mass distribution particularly suitable for blow molding films having a thickness in the range from 8 to 200 μm. The molding composition has a density at a temperature of 23° C. in the range from 0.948 to 0.953 g/cm | 07-14-2011 |
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| 20080250285 | Circuit Arrangement, Electronic Mechanism, Electrical Turn out and Procedures for the Operation of One Circuit Arrangement - A circuit arrangement may include a scan test input stage having a test input for receiving a test signal, wherein the scan test input stage can be switched in high-impedance state; a data input stage having a data input for receiving a data signal, wherein the data input stage can be switched in high-impedance state. The circuit arrangement may further include a latch coupled to at least one output of the scan test input stage and to at least one output of the data input stage; and a drive circuit, which is configured to generate a pulsed clock signal for the data input stage and a signal for driving the scan test input stage. | 10-09-2008 |
| 20090115468 | Integrated Circuit and Method for Operating an Integrated Circuit - An integrated circuit, comprising a first data retention element configured to retain the data, the first data retention element having a first setup time, and a second data retention element configured to retain the data, the second data retention element having a second setup time, the second data retention element further having a data input. The second data retention element is connected in parallel with the first data retention element, and the second data retention element is configurable via the data input such that the second setup time is longer than the first setup time. | 05-07-2009 |
| 20090189702 | CIRCUIT AND METHOD FOR DETECTING A VOLTAGE CHANGE - A circuit arrangement for detecting voltage changes, comprising supply terminals configured to apply a first potential and a second potential, a first oscillator and a second oscillator, which are operated with the first potential and the second potential, a voltage dependence of the frequency of the first oscillator differing from a voltage dependence of the frequency of the second oscillator, a first evaluation circuit configured to evaluate the frequency of the first oscillator and a second evaluation circuit configured to evaluate the frequency of the second oscillator, and a comparison circuit configured to compare a value based on the evaluated frequencies of the first oscillator and of the second oscillator with a predetermined threshold value, and to output a voltage change signal indicating an impermissible voltage change between the first potential and the second potential depending on the result of the comparison. | 07-30-2009 |
