| Patent application number | Description | Published |
|---|
| 20080231295 | DEVICE AND METHOD FOR ELECTRICAL CONTACTING SEMICONDUCTOR DEVICES FOR TESTING - A device and method are disclosed for electrical contacting of semiconductor devices for testing. One embodiment provides for testing semiconductor devices or integrated circuits, including a probe card with contact tips for the electrical contacting of the semiconductor devices. The electrical connection of at least one contact tip to the test system is adapted to be switched via a resistively switching memory cell. A resistively switching memory cell in the form of a nano switch is integrated in the electrical connection of the contact tip. | 09-25-2008 |
| 20080231303 | SEMICONDUCTOR DEVICE FOR ELECTRICAL CONTACTING SEMICONDUCTOR DEVICES - A semiconductor device with a number of contact pads for the electrical contacting of the semiconductor device is disclosed. A padding layer, which is manufactured of a hard material, is provided at least partially below an upper layer of the contact pads. | 09-25-2008 |
| 20080247217 | Integrated circuit, memory cell array, memory module, method of operating an integrated circuit, and computing system - An integrated circuit includes a plurality of resistivity changing memory cells and a plurality of resistivity changing reference cells. The integrated circuit is arranged such that each memory cell is switchable between N resistance levels, N being an integer greater than or equal to 2. To each of at least two possible resistance levels of a memory cell an individual reference cell as assigned. A resistance level of a memory cell is determined or set depending on the resistance level of the reference cell which is assigned to the resistance level of the memory cell. | 10-09-2008 |
| 20080259676 | Integrated Circuit, Memory Module, Method of Operating an Integrated Circuit, Method of Manufacturing an Integrated Circuit, and Computer Program Product - According to one embodiment of the present invention, an integrated circuit is provided which includes a plurality of resistivity changing cells. At least two resistance ranges are assigned to each resistivity changing cell, each resistance range defining a possible state of the resistivity changing cell. The integrated circuit is operable in a cell initializing mode in which initializing signals are applied to the resistivity changing cells. The strengths and durations of the initializing signals are chosen such that the resistance of each resistivity changing cell is shifted into one of the resistance ranges assigned to the resistivity changing cell. | 10-23-2008 |
| 20080263415 | Integrated Circuit, Memory Module, Method of Operating an Integrated Circuit, Method of Fabricating an Integrated Circuit, Computer Program Product, and Computing System - According to one embodiment of the present invention, an integrated circuit includes a plurality of memory cells, the integrated circuit being operable in a memory cell testing mode in which testing signals are applied to the memory cells, wherein the strengths and durations of the testing signals at least partly differ from the strengths and durations of programming signals or sensing signals used for programming and sensing memory states of the memory cells. | 10-23-2008 |
| 20090050870 | INTEGRATED CIRCUIT INCLUDING MEMORY ELEMENT WITH SPATIALLY STABLE MATERIAL - An integrated circuit includes a heater element serving as a first electrode, a second electrode, a memory element comprising resistance changing material coupled to the heater element and to the second electrode, and a diffusion compensation region coupled to the heater element and to the resistance changing material. The diffusion compensation region includes a surplus of at least one diffusible species present in the memory element and provides at least one diffusible species to the memory element. | 02-26-2009 |
| 20090052232 | METHOD FOR FABRICATING AN INTEGRATED CIRCUIT INCLUDING MEMORY ELEMENT WITH SPATIALLY STABLE MATERIAL - A method for fabricating an integrated circuit, the method comprises forming a first electrode, depositing resistance changing material over the first electrode, the resistance changing material having an active zone for switching the resistance of the resistance changing material and an inactive zone, and forming a second electrode over the resistance changing material. The chemical composition of the resistance changing material in the active zone differs from the chemical composition of the resistance changing material in the inactive zone | 02-26-2009 |
| 20090161415 | INTEGRATED CIRCUIT FOR SETTING A MEMORY CELL BASED ON A RESET CURRENT DISTRIBUTION - An integrated circuit includes an array of resistance changing memory cells and a first circuit. The first circuit is configured to set a selected memory cell to a crystalline state by applying a decreasing stair step pulse to the selected memory cell. The pulse is based on a reset current distribution for the array of memory cells. | 06-25-2009 |
| 20090295443 | System and Method For Modifying Signal Characteristics - The present invention embodiments provide a system to modify signal characteristics to produce a desired signal. The system comprises a signal module to modify signal characteristics. The signal module includes at least one input to receive an input signal including a substantially rectangular signal and one or more control signals and an output to provide a substantially trapezoidal signal. A signal unit of the signal module adjusts characteristics of the substantially rectangular signal including leading and/or trailing edges of that signal in accordance with the one or more control signals to produce the substantially trapezoidal signal. The present invention embodiments further include a probe card and method to adjust signal characteristics as described above. | 12-03-2009 |
| 20090310401 | INTEGRATED CIRCUIT INCLUDING A MEMORY ELEMENT PROGRAMMED USING A SEED PULSE - An integrated circuit includes a resistance changing memory element and a circuit. The circuit is configured to program the memory element to a crystalline state from an amorphous state by applying a seed pulse to the memory element followed by a set pulse. | 12-17-2009 |
| 20100084741 | Integrated Circuit - According to an embodiment, an integrated circuit including a plurality of resistance changing memory cells is disclosed. Each memory cell includes a first electrode, a second electrode and resistance changing memory element arranged between the first electrode and the second electrode. A front surface area of an end section of the first electrode that faces the resistance changing memory element is smaller than a front surface area of an end section of the second electrode that faces the resistance changing memory element. | 04-08-2010 |
