Patent application number | Description | Published |
20090208865 | PHOTOLITHOGRAPHY FOCUS IMPROVEMENT BY REDUCTION OF AUTOFOCUS RADIATION TRANSMISSION INTO SUBSTRATE - An anti-reflective coating material, a microelectronic structure that includes an anti-reflective coating layer formed from the anti-reflective coating material and a related method for exposing a resist layer located over a substrate while using the anti-reflective coating layer provide for attenuation of secondary reflected vertical alignment beam radiation when aligning the substrate including the resist layer located thereover. Such enhanced vertical alignment provides for improved dimensional integrity of a patterned resist layer formed from the resist layer, as well as additional target layers that may be fabricated while using the resist layer as a mask. | 08-20-2009 |
20090265679 | SYSTEM AND METHOD OF PREDICTING PROBLEMATIC AREAS FOR LITHOGRAPHY IN A CIRCUIT DESIGN - A system and method is provided which predicts problematic areas for lithography in a circuit design, and more specifically, which uses modeling data from a modeling tool to accurately predict problematic lithographic areas. The method includes identifying surface heights of plurality of tiles of a modeled wafer, and mathematically mimicking a lithographic tool to determine best planes of focus for exposure for the plurality of tiles. | 10-22-2009 |
20110256486 | PHOTOLITHOGRAPHY FOCUS IMPROVEMENT BY REDUCTION OF AUTOFOCUS RADIATION TRANSMISSION INTO SUBSTRATE - An anti-reflective coating material, a microelectronic structure that includes an anti-reflective coating layer formed from the anti-reflective coating material and a related method for exposing a resist layer located over a substrate while using the anti-reflective coating layer provide for attenuation of secondary reflected vertical alignment beam radiation when aligning the substrate including the resist layer located thereover. Such enhanced vertical alignment provides for improved dimensional integrity of a patterned resist layer formed from the resist layer, as well as additional target layers that may be fabricated while using the resist layer as a mask. | 10-20-2011 |
20120254812 | SYSTEM AND METHOD OF PREDICTING PROBLEMATIC AREAS FOR LITHOGRAPHY IN A CIRCUIT DESIGN - A system and method is provided which predicts problematic areas for lithography in a circuit design, and more specifically, which uses modeling data from a modeling tool to accurately predict problematic lithographic areas. The method includes identifying surface heights of plurality of tiles of a modeled wafer, and mathematically mimicking a lithographic tool to determine best planes of focus for exposure for the plurality of tiles. | 10-04-2012 |
20130286370 | SYSTEM AND METHOD OF PREDICTING PROBLEMATIC AREAS FOR LITHOGRAPHY IN A CIRCUIT DESIGN - A system and method is provided which predicts problematic areas for lithography in a circuit design, and more specifically, which uses modeling data from a modeling tool to accurately predict problematic lithographic areas. The method includes identifying surface heights of plurality of tiles of a modeled wafer, and mathematically mimicking a lithographic tool to determine best planes of focus for exposure for the plurality of tiles. | 10-31-2013 |
20140071416 | METHOD AND SYSTEM TO PREDICT LITHOGRAPHY FOCUS ERROR USING SIMULATED OR MEASURED TOPOGRAPHY - A method and system to predict lithography focus error using chip topography data is disclosed. The chip topography data may be measured or simulated topography data. A plane is best fitted to the topography data, and residuals are computed. The residuals are then used to make a prediction regarding the focus error. The density ratio of metal to dielectric may also be used as a factor in determining the predicted focus error. | 03-13-2014 |
20140075396 | METHOD AND SYSTEM TO PREDICT LITHOGRAPHY FOCUS ERROR USING SIMULATED OR MEASURED TOPOGRAPHY - A method and system to predict lithography focus error using chip topography data is disclosed. The chip topography data may be measured or simulated topography data. A plane is best fitted to the topography data, and residuals are computed. The residuals are then used to make a prediction regarding the focus error. The density ratio of metal to dielectric may also be used as a factor in determining the predicted focus error. | 03-13-2014 |
20140075399 | METHOD AND SYSTEM TO PREDICT LITHOGRAPHY FOCUS ERROR USING SIMULATED OR MEASURED TOPOGRAPHY - A method and system to predict lithography focus error using chip topography data is disclosed. The chip topography data may be measured or simulated topography data. A plane is best fitted to the topography data, and residuals are computed. The residuals are then used to make a prediction regarding the focus error. The density ratio of metal to dielectric may also be used as a factor in determining the predicted focus error. | 03-13-2014 |