| Patent application number | Description | Published |
|---|
| 20100174885 | RECONFIGURABLE PROCESSOR AND OPERATING METHOD OF THE SAME - Provided are a reconfigurable processor and operating method thereof. The reconfigurable processor may use a configuration memory distributed to each operation unit. The distributed configuration memory may be separated into a distributed operation configuration memory including configuration information about an operation of a function unit, and a distributed routing configuration memory including configuration information about routing. The distributed operation configuration memory may be activated according to a predicate signal. | 07-08-2010 |
| 20100185839 | APPARATUS AND METHOD FOR SCHEDULING INSTRUCTION - An apparatus and method for scheduling an instruction are provided. The apparatus includes an analyzer configured to analyze dependency of a plurality of recurrence loops and a scheduler configured to schedule the recurrence loops based the analyzed dependencies. When scheduling a plurality of recurrence loops, the apparatus first schedules a dominant loop whose loop head has no dependency on another loop among the recurrence loops. | 07-22-2010 |
| 20100199068 | RECONFIGURABLE PROCESSOR FOR REDUCED POWER CONSUMPTION AND METHOD THEREOF - Described herein is a reconfigurable processor which uses a distributed configuration memory structure and an operation method thereof in which power consumption is reduced. A processing unit which configures the reconfigurable processor includes a functional unit, a distributed configuration memory, a no-operation (NOP) register, and a controller. The NOP register stores information which represents whether or not a NOP operation is performed at each clock cycle. The controller controls to deactivate the distributed configuration memory at a clock cycle at which a NOP operation is performed. | 08-05-2010 |
| 20100199069 | SCHEDULER OF RECONFIGURABLE ARRAY, METHOD OF SCHEDULING COMMANDS, AND COMPUTING APPARATUS - A scheduler of a reconfigurable array, a method of scheduling commands, and a computing apparatus are provided. To perform a loop operation in a reconfigurable array, a recurrence node, a producer node, and a predecessor node are detected from a data flow graph of the loop operation such that resources are assigned to such nodes so as to increase the loop operating speed. Also, a dedicated path having a fixed delay may be added to the assigned resources. | 08-05-2010 |
| 20100199076 | COMPUTING APPARATUS AND METHOD OF HANDLING INTERRUPT - A computing apparatus and method of handling an interrupt are provided. The computing apparatus includes a coarse-grained array, a host processor, and an interrupt supervisor. When an interrupt occurs in the coarse-grained array while performing a loop operation, the host processor processes the interrupt, and the interrupt supervisor may perform mode switching between the coarse-grained array and the host processor. | 08-05-2010 |
| 20100211759 | APPARATUS AND METHOD FOR GENERATING VLIW, AND PROCESSOR AND METHOD FOR PROCESSING VLIW - An apparatus and method for generating a very long instruction word (VLIW) command that supports predicated execution, and a VLIW processor and method for processing a VLIW are provided herein. The VLIW command includes an instruction bundle formed of a plurality of instructions to be executed in parallel and a single value indicating predicated execution, and is generated using the apparatus and method for generating a VLIW command. The VLIW processor decodes the instruction bundle and executes the instructions, which are included in the decoded instruction bundle, in parallel, according to the value indicating predicated execution. | 08-19-2010 |
| 20100223449 | INTERRUPT HANDLING APPARATUS AND METHOD FOR EQUAL-MODEL PROCESSOR AND PROCESSOR INCLUDING THE INTERRUPT HANDLING APPARATUS - An interrupt support determining apparatus and method for an equal-model processor, and a processor including the interrupt support determining apparatus are provided. The interrupt support determining apparatus determines whether an instruction input to a processor decoder is a multiple latency instruction, compares a current latency of the instruction with a remaining latency if the instruction is a multiple latency instruction, and updates the current latency to the remaining latency if the current latency is greater than the remaining latency. | 09-02-2010 |
| 20100274939 | RECONFIGURABLE PROCESSOR AND INTERRUPT HANDLING METHOD - An interrupt handling technology and a reconfigurable processor are provided. The reconfigurable processor includes a plurality of processing elements, and some of the processing elements are designated for interrupt handling. When an interrupt request occurs while the reconfigurable processor is executing a loop operation, the designated processing elements may process the interrupt request. The interrupt handling technology allows the interrupt request and the loop operation to be processed in parallel. | 10-28-2010 |
