| Patent application number | Description | Published |
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| 20110259904 | COVER FOR DISPLAY STRUCTURES - A jacket structure for mounting to a display structure, the jacket structure comprising one or more panels having an inner side and an outer side with regards to the display structure, one or more members corresponding to columns of the display structure, one or more elements corresponding to a tray base of the display structure, the elements corresponding to a tray base of the display structure intersecting with the members corresponding to columns of the display structure, the intersection of the members corresponding to the column of the display structure and the elements corresponding to the tray base of the display structure forming a window through which a consumer can reach out to grab the product within the display structure, a horizontal flap in an upper side of the element corresponding to a tray base and a horizontal flap in a lower side of the element corresponding to a tray base, wherein the flaps are configured to form a locked tab structure when the jacket structure is in a mounted position, and vertical flaps formed from the parts corresponding to the column of the display structure towards the window, wherein the vertical flaps are configured to form a locked tab structure when the jacket structure in a mounted position. | 10-27-2011 |
| 20120248949 | PRODUCT EXHIBITION STRUCTURE AND ASSEMBLY AND DISASSEMBLY METHOD THEREOF - A collapsible and folding showcase used to load and exhibit products, that is comprised of a base with at least three sides, each side with two extremes, each extreme of a side is jointed with another extreme of another side then forming corners between the extremes; a top with at least three sides, each side with two extremes, each extreme of a side is jointed with another extreme of another side then forming corners between the extremes; at least three posts, each post with a lower extreme and an upper extreme, each post can be set up in a corner of the base through the upper extreme of the post, each post can be coupled through the upper extreme of the post with a corner of the top, each pair of posts proximate to one another and coupled with one another and within them at least a base of tray, then forming, between the pair of proximate posts and the at least one base of the tray, a shelf, the at least one base of tray positioned between the lower extreme and the upper extreme of the post; at least one tray for each base of tray, the tray can rest on the base of the tray. | 10-04-2012 |
| 20120267329 | AUTO-ADJUSTABLE POSITION EXHIBITOR - A showcase for the loading and exhibition of products, that is comprised of a frame with two lateral walls and a lower wall, where each lateral wall has at least a first and a second hole, a rear support with two arms and a lower joint, where each arm has at least a first hole, where the first hole of the frame is collinear with the first hole of the rear support in a convergence point between the frame and the rear support; and at least one shelf or rack with two lateral walls and a front joint, the shelf or rack being rotational between a first position and a second position when it is set up with the frame and the rear support. | 10-25-2012 |
| 20130055604 | COLLAPSIBLE DISPLAY STRUCTURE - A telescopic display structure is disclosed, the structure having a number of columns each having two or more substantially hollow parts, each part having two ends, a first part having a first width and an opening proximate to an upper end and a second part having a second width and an opening proximate to a lower end, the two widths of the two parts being different, so that at least part of the second part may slide within the first part, the grooves or openings having the same direction in regards to the display structure and being co-lineal when the telescopic display structure is in an extended position. A tray base having faces is fixed to the column. A resilient device having resilient parts is placed within the lower end of the second part of the columns, one the parts of the resilient device having a protuberance with the same direction as the openings and with a length such that said protuberance passes through the openings of the parts of the column when the protuberance is co-lineal with said openings and when the telescopic display structure is in an extended position. | 03-07-2013 |
| 20130062297 | FOLDABLE PRODUCT DISPLAY STRUCTURE - A display structure has a base with non-rotatable sides and rotatable sides containing a first part with and a second part, the parts fastened by a rotatable fastener; a post containing a first and second face, the two non-rotatable sides fastened to the lower end of the posts, and the rotatable sides fastened to the lower end of the posts, a rotatable fastening means specially located so as to allow rotation of the parts in regards to the post; and a top with non-rotatable and rotatable sides, the non-rotatable sides of the top fastened to the top of the post, the rotatable side of the top fastened to the non-rotatable sides of the top with rotatable fastening means, said rotatable fastening means of the top are specially located to allow rotation of the parts in regards to the non-rotatable side. | 03-14-2013 |
| Patent application number | Description | Published |
|---|
| 20110131444 | SYSTEMS AND METHODS FOR LOW WEAR OPERATION OF SOLID STATE MEMORY - This disclosure is related to systems and methods for low wear operation of solid state memory, such as a flash memory. In one example, a controller is coupled to a memory and adapted to dynamically adjust programming thresholds over the course of usage of the data storage device such that a signal-to-noise ratio from reading data stored in the data storage cells is no less than a minimum amount needed to recover the data using an enhanced error detection capability. | 06-02-2011 |
| 20110181978 | DISC DRIVE DATA RECOVERY UTILIZING OFF CENTER TRACK INFORMATION - Disc drive data recovery methods and systems that utilize off center track information are provided. A disc drive data track is illustratively read at a first position along a width of the data track and at a second position along the width of the data track. The data read from the track is stored and tagged with indications of the first and the second positions. The tagged data is optionally used to calculate average waveforms for each of the first and the second positions and to identify the average waveform having the highest signal-to-noise ratio. | 07-28-2011 |
| 20110191654 | ADJUSTABLE ERROR CORRECTION CODE LENGTH IN AN ELECTRICAL STORAGE DEVICE - An apparatus includes a memory that is allocated to reported portions and overprovisioned portions. The apparatus includes an error correction circuit that communicates with the memory in error correction coded data that has a controllable ECC length. The ECC length is a function of a history of error reports. A memory allocation engine balances a size of the overprovisioned portions to maintain a size of the reported portions. The balancing is performed as a function of an average of ECC lengths in the ECC length table over a time interval in which a size of the memory decreases with accumulated erase cycles of the memory. | 08-04-2011 |
| 20110296272 | OUTER CODE PROTECTION FOR SOLID STATE MEMORY DEVICES - Outer code words can span multiple data blocks, multiple die, or multiple chips of a memory device to protect against errors in the data stored in the blocks, die and/or chips. A solid state memory device is arranged in multiple data blocks, each block including an array of memory cells arranged in a plurality of pages. The data is encoded into inner code words and symbol-based outer code words. The inner code words and the symbol-based outer code words are stored in the memory cells of the multiple blocks. One or more inner code words are stored in each page of each block and one or more symbols of each outer code word are stored in at least one page of each block. The inner code words and the outer code words are read from the memory device and are used to correct the errors in the data. | 12-01-2011 |
| 20110296273 | METHODS AND DEVICES TO REDUCE OUTER CODE FAILURE RATE VARIABILITY - The variability of outer code failure rate of memory pages of a solid state memory device can be reduced by selectively grouping the pages included in the outer code words. The data in the page groups are encoded into outer code words which are stored in the memory device. Encoding the data of the page groups and storing the encoded data includes intermittently accumulating an outer code parity as the pages are sequentially stored in the memory device according to a particular order. The pages can be randomly selected for the page groups or can be grouped based on predicted or measured failure rate information. In a memory device having multi-level memory cells, predicting the failure rate of a page can be based on whether the page is a most significant bit (MSB) page or a least significant bit (LSB) page. | 12-01-2011 |
| 20120023144 | Managing Wear in Flash Memory - At least two groupings are established for a plurality of erase units. The erase units include flash memory units that are available for writing subsequent to erasure. The groupings are based at least on a recent write frequency of data targeted for writing to the erase units. A wear criteria is determined for each of the erase units and the erase units are assigned to one of the respective groupings based on the wear criteria of the respective erase units and further based on a wear range assigned to each of the at least two groupings. | 01-26-2012 |
| 20120023282 | Multi-Tier Address Mapping in Flash Memory - A user data portion of a flash memory arrangement is grouped into a plurality of mapping units. Each of the mapping units includes a user data memory portion and a metadata portion. The mapping units form a plurality of groups that are associated with at least one lower tier of a forward memory map. For each of the groups, a last written mapping unit within the group is determined. The last written mapping unit includes mapping data in the metadata portion that facilitates determining a physical address of other mapping units within the group. A top tier of the forward memory map is formed that includes at least physical memory locations of the last written mapping units of each of the groups. A physical address of a targeted memory is determined using the top tier and the metadata of the at least one lower tier. | 01-26-2012 |
| 20120075930 | REUSE OF INFORMATION FROM MEMORY READ OPERATIONS - A nominal reference read operation compares analog voltages of the memory cells to at least one nominal reference voltage. A shifted reference read operation compares the analog voltages of the memory cells to at least one shifted reference voltage that is shifted from the nominal reference voltage to compensate for an expected change in the analog voltages of the memory cells. Data stored in the memory cells is decoded by a first decoding process that uses the information from either the nominal reference read operation or the shifted reference read operation. The data stored in the memory cells is decoded by a second decoding process that uses the information from both the nominal reference read operation and the shifted reference read operation. | 03-29-2012 |
| 20120079355 | OPPORTUNISTIC DECODING IN MEMORY SYSTEMS - Approaches for decoding data read from memory cells of a nonvolatile, solid state memory involve attempting to decode hard data using a hard decoding process prior to a time that soft data is available to the decoder. The hard data includes information about the digital symbols stored in the memory cells without data confidence information. The soft data includes information about the digital symbols stored in the memory cells and data confidence information. In response to the hard decoding process failing to achieve convergence, after the soft data becomes available to the decoder, the soft data is decoded using a soft decoding process. The decoder generates an output of the decoded data after the hard decoding process or the soft decoding process achieves convergence. | 03-29-2012 |
| 20120110239 | Causing Related Data to be Written Together to Non-Volatile, Solid State Memory - A first write request that is associated with a first logical address is received via a collection of write requests targeted to a non-volatile, solid state memory. It is determined whether the logical address is related to logical addresses of one or more other write requests of the collection that are not proximately ordered with the first write request in the collection. In response to this determination, the first write request and the one or more other write requests are written together to the memory. | 05-03-2012 |
| 20120176698 | Reducing Errors Resulting from Width Variability of Storage Media Write Tracks - Various approaches that reduce the width variability of storage media data tracks are described. First and second data tracks are written so that the second track overlaps the first track. After writing the second track data to the second track, an effective width of the first track is determined. The effective width of the first track is the portion of the first track that is not overlapped by the second track. One or more additional write operations to the recording medium are performed to compensate for the effective width of the first track being less than a threshold. The additional write operations may include one or more of rewriting the first track data to a third track on the storage medium and writing additional redundancy information to supplement the coding of the first track data. | 07-12-2012 |
| 20120278679 | Iterating Inner and Outer Codes for Data Recovery - A storage medium includes at least one data unit defining a plurality of symbol-based inner code words and a plurality of symbol-based outer code words. Each symbol included in one of the inner code words is also included in one of the outer code words. A processor is configured to perform a first iteration of inner code error correction on the plurality of symbol-based inner code words, a first iteration of outer code error correction on the plurality of symbol-based outer code words and a second iteration of inner code error correction on the plurality of symbol-based inner code words. In the first iteration of outer code error corrections, at least one of the outer code words is correctable. In the second iteration of inner code error correction, at least one of the inner code words is correctable. | 11-01-2012 |
| 20120304037 | OUTER CODE ERROR CORRECTION - Values are grouped into a first set of groupings of values. Based on inner codes, the number of groupings in the first set of groupings that have at least one erroneous value is determined. If the number of groupings in the first set of groupings that have an erroneous value is fewer than a maximum number of groupings that can be corrected by outer codes, a seek operation is begun. During the seek operation, the outer codes are used to detect and correct the erroneous values that were produced during the reading of values. In other aspects, a parity section for a data section of a data storage device is dirtied before writing any data to the data section such that if writing to the data section is interrupted, the parity section will indicate that it should not be used to correct data read from the data section. | 11-29-2012 |
| 20130061019 | STORAGE CONTROL SYSTEM WITH WRITE AMPLIFICATION CONTROL MECHANISM AND METHOD OF OPERATION THEREOF - A method of operation of a storage control system includes: partitioning logical addresses into a number of subdrives, the logical addresses associated with a memory device; and monitoring a data write measure of one of the subdrives. | 03-07-2013 |
| 20130061101 | NON-VOLATILE MEMORY MANAGEMENT SYSTEM WITH LOAD LEVELING AND METHOD OF OPERATION THEREOF - A method of operation of a non-volatile memory system includes: generating a test stimulus for a page in a memory array; measuring a test response from the page in the memory array based on the test stimulus; calculating a measured effective life of the page from the test response; and determining a use plan according to the measured effective life for accessing the page. | 03-07-2013 |
| 20130086454 | ADJUSTABLE MEMORY ALLOCATION BASED ON ERROR CORRECTION - An apparatus may comprise a memory including a first area of total usable storage capacity of the memory reported to a host device, a second area occupied by error correction code (ECC) appended to data stored in the first area, and a third area of usable data storage capacity not reported to the host device. The apparatus may further comprise a controller configured to balance sizes of the second area and third area to maintain a size of the first area as the length of ECC of data stored in the first area increases. The controller may be further configured to exchange data having an ECC of a controllable length with the memory based on a data storage location, and adjust the controllable length of the ECC based on an error history of the data storage location. | 04-04-2013 |
