| Patent application number | Description | Published |
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| 20090187697 | Execute-Only Memory and Mechanism Enabling Execution From Execute-Only Memory for Minivisor - In one embodiment, a processor comprises an execution core configured to execute instructions; and a register configured to store an execute-only valid indication indicative of whether or not execution of instructions is permitted in pages that are indicated as execute-only in a set of page tables used by the processor for address translation. The execution core is configured, responsive to a fetch within an execute-only page, to signal a fault responsive to the execute-only valid indication indicating that execution is not permitted in the execute-only page, and wherein the execution core is configured to permit the fetch within the execute-only page responsive to the execute-only valid indication indicating that execution is permitted in the execute-only page. | 07-23-2009 |
| 20090187698 | Minivisor Entry Point in Virtual Machine Monitor Address Space - In one embodiment, a processor supports an alternate address space during execution of non-guest code (such as a minivisor or a virtual machine monitor (VMM)). The alternate address space may be the guest address space. An instruction in the minivisor/VMM may specify the alternate address space for a data access, permitting the minivisor/VMM to read guest memory state via the alternate address space. In another embodiment, a processor may implement a page table base address register dedicated for the minivisor's use. In still another embodiment, the minivisor may be implemented as a specified entry point in the VMM address space. | 07-23-2009 |
| 20090187726 | Alternate Address Space to Permit Virtual Machine Monitor Access to Guest Virtual Address Space - In one embodiment, a processor supports an alternate address space during execution of non-guest code (such as a minivisor or a virtual machine monitor (VMM)). The alternate address space may be the guest address space. An instruction in the minivisor/VMM may specify the alternate address space for a data access, permitting the minivisor/VMM to read guest memory state via the alternate address space. In another embodiment, a processor may implement a page table base address register dedicated for the minivisor's use. In still another embodiment, the minivisor may be implemented as a specified entry point in the VMM address space. | 07-23-2009 |
| 20090187729 | Separate Page Table Base Address for Minivisor - In one embodiment, a processor supports an alternate address space during execution of non-guest code (such as a minivisor or a virtual machine monitor (VMM)). The alternate address space may be the guest address space. An instruction in the minivisor/VMM may specify the alternate address space for a data access, permitting the minivisor/VMM to read guest memory state via the alternate address space. In another embodiment, a processor may implement a page table base address register dedicated for the minivisor's use. In still another embodiment, the minivisor may be implemented as a specified entry point in the VMM address space. | 07-23-2009 |
| 20090187902 | Caching Binary Translations for Virtual Machine Guest - In one embodiment, a method comprises in response to an intercept of a first instruction in a guest that is controlled by a virtual machine monitor (VMM), updating first tracking data corresponding to the first instruction in an intercept tracking table; determining, from the first tracking data, that a translation of the first instruction into a first routine is to be performed; and caching the first routine to be executed in response to a subsequent intercept of the first instruction, wherein the first routine is formed from instructions defined in a same instruction set architecture as the first instruction. In some embodiments, a routine for an intercepted instruction that is within a merge window of the first instruction in a guest may be merged into the same routine with the first instruction. | 07-23-2009 |
| 20090187904 | Redirection Table for Virtual Machine Guest - In one embodiment, a processor comprises a redirect unit configured to detect a match of an instruction pointer (IP) in an IP redirect table, the IP corresponding to a guest instruction that the processor has intercepted, wherein the guest is executed under control of a virtual machine monitor (VMM), and wherein the redirect unit is configured to redirect instruction fetching by the processor to a routine identified in the IP redirect table instead of exiting to the VMM in response to the intercept of the guest instruction. | 07-23-2009 |
| 20100191885 | Guest Interrupt Controllers for Each Processor to Aid Interrupt Virtualization - In one embodiment, a system comprises a processor, a first interrupt controller coupled to the processor, and a second interrupt controller coupled to the processor. The first interrupt controller is configured to signal the processor for an interrupt in response to receiving a first interrupt message communicating a first interrupt that is targeted at a host in the system. The second interrupt controller is configured to signal the processor for an interrupt in response to receiving a second interrupt message communicating a second interrupt that is targeted at a guest that is controlled by the host and that is executable on the processor. | 07-29-2010 |
| 20100191887 | Monitoring Interrupt Acceptances in Guests - In one embodiment, an interrupt acceptance control circuit is provided. The interrupt acceptance control circuit may monitor one or more guest interrupt controllers in a system in response to an IPI (or device interrupt) issued in a guest, to determine if each targeted vCPU in the guest has accepted the interrupt. If not, the interrupt acceptance control circuit may communicate the lack of acceptance to the VMM, in one embodiment. The VMM may attempt to schedule the vCPUs that have not accepted the interrupt, for example. | 07-29-2010 |
| 20100191888 | Guest Interrupt Manager to Aid Interrupt Virtualization - In an embodiment, a system comprises a memory system and a guest interrupt manager. The guest interrupt manager is configured to receive an interrupt message corresponding to an interrupt that is targeted at a guest executable on the system. The guest interrupt manager is configured to record the interrupt in a data structure in the memory system to ensure that the interrupt is delivered to the guest even if the guest is not active in the system at a time that the interrupt message is received. | 07-29-2010 |
| 20100191889 | MEMORY STRUCTURE TO STORE INTERRUPT STATE FOR INACTIVE GUESTS - In an embodiment, a system comprises a memory system configured to store a data structure. The data structure stores at least an interrupt request state for each destination in each of a plurality of guests executable on the system. The interrupt request state identifies which interrupts have been requested at the corresponding interrupt controller in the corresponding guest of the plurality of guests. A guest interrupt manager is coupled to receive an interrupt message targeted at a first destination in a first guest of the plurality of guests, and the guest interrupt manager is configured to update the interrupt request state in the data structure that corresponds to the first destination and the first guest. | 07-29-2010 |
| 20100223447 | Translate and Verify Instruction for a Processor - In an embodiment, a first instruction is defined that comprises at least a first operand from which the execution core is configured to determine a virtual address and a second operand that specifies one or more translation attributes that exist in a page table entry that defines a translation for the virtual address. A processor executing the instruction translates the virtual address, verifies whether or not the translation attributes in the page table entry match the specified translation attributes, faults the first instruction responsive to failing to locate a translation for the virtual address, and responsive to locating a translation for the virtual address in the page table entry but with the translation attributes in the entry failing to match the specified translation attributes. | 09-02-2010 |
| 20110010707 | VIRTUAL MACHINE DEVICE AND METHODS THEREOF - A data processing device includes one or more state registers to store state information associated with an execution core of the device. Each state register includes an associated “dirty” bit. When a guest program is executed at the execution core, a dirty bit is set in response to a change in the state information at the associated state register. In response to a world switch from the guest program to a VMM, the state information at each state register is stored to memory only if the associated dirty bit is set. In addition, if the VMM changes any stored state information, it clears a “clean” bit associated with the changed information. In response to a world switch from the VMM to a guest, the state information associated with cleared clean bits is retrieved from memory. | 01-13-2011 |
| 20110055523 | EARLY BRANCH DETERMINATION - A method and apparatus for branch determination. The method includes a first command issuing within a computer processor, wherein execution of the first command by the computer processor includes evaluating one or more conditions to set one or more flags. The method further includes a second command issuing, subsequent to the first command issuing, within the computer processor, wherein execution of the second command by the computer processor includes causing the computer processor to wait until the one or more flags are set. Subsequent to the first and second commands issuing, the method includes a third command issuing within the computer processor, wherein execution of the third command by the computer processor includes performing a jump operation based on a value of at least one of the one or more flags set by the first command. | 03-03-2011 |
| 20110107328 | VIRTUAL MACHINE DEVICE AND METHODS THEREOF - A data processing device is configured such that, during a loop executed by a guest, the device executes a PAUSE instruction. In response to executing a PAUSE instruction, the data processing device determines a relationship between the current PAUSE instruction and a previously executed PAUSE instruction. For example, the data processing device can determine the amount of time that has elapsed between the PAUSE instructions. Based on the relationship between the current and previous pause instructions, the data processing device can reset the counter to a reset value, or adjust (i.e. increment or decrement) the counter by a defined amount. | 05-05-2011 |
| 20110161955 | HYPERVISOR ISOLATION OF PROCESSOR CORES - Techniques for utilizing processor cores include sequestering processor cores for use independently from an operating system. In at least one embodiment of the invention, a method includes executing an operating system on a first subset of cores including one or more cores of a plurality of cores of a computer system. The operating system executes as a guest under control of a virtual machine monitor. The method includes executing work for an application on a second subset of cores including one or more cores of the plurality of cores. The first and second subsets of cores are mutually exclusive and the second subset of cores is not visible to the operating system. In at least one embodiment, the method includes sequestering the second subset of cores from the operating system. | 06-30-2011 |
