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Bencher, CA

Chris D. Bencher, San Jose, CA US

Patent application numberDescriptionPublished
20080230154ABSORBER LAYER FOR DSA PROCESSING - A method of processing a substrate comprising depositing a layer comprising amorphous carbon on the substrate and then laser annealing the substrate is provided. Optionally, the layer further comprises a dopant selected from the group consisting of nitrogen, boron, phosphorus, fluorine, and combinations thereof. In one aspect, the layer comprising amorphous carbon is an anti-reflective coating and an absorber layer that absorbs electromagnetic radiation emitted by the laser and anneals a top surface layer of the substrate.09-25-2008

Patent applications by Chris D. Bencher, San Jose, CA US

Christopher Dennis Bencher, San Jose, CA US

Patent application numberDescriptionPublished
20080197109Etch pattern definition using a CVD organic layer as an anti-reflection coating and hardmask - A multilayer antireflective hard mask structure is disclosed. The structure comprises: (a) a CVD organic layer, wherein the CVD organic layer comprises carbon and hydrogen; and (b) a dielectric layer over the CVD organic layer. The dielectric layer is preferably a silicon oxynitride layer, while the CVD organic layer preferably comprises 70-80% carbon, 10-20% hydrogen and 5-15% nitrogen. Also disclosed are methods of forming and trimming such a multilayer antireflective hard mask structure. Further disclosed are methods of etching a substrate structure using a mask structure that contains a CVD organic layer and optionally has a dielectric layer over the CVD organic layer.08-21-2008
20080257864Methods and devices to reduce defects in dielectric stack structures - A variety of techniques may be employed alone or in combination to reduce the incidence of defects arising in dielectric stack structures formed by chemical vapor deposition (CVD). Incidence of a first defect type attributable to reaction between an unreacted species of a prior CVD step and reactants of a subsequent CVD step, is reduced by exposing a freshly-deposited dielectric layer to a plasma before any additional layers are deposited. Incidence of a second defect type attributable to the presence of incompletely vaporized CVD liquid precursor material, is reduced by exposing the freshly-deposited dielectric layer to a plasma, and/or by continuing the flow of carrier gas through an injection valve for a period beyond the conclusion of the CVD step.10-23-2008
20090111281FREQUENCY DOUBLING USING A PHOTO-RESIST TEMPLATE MASK - A method for doubling the frequency of a lithographic process using a photo-resist template mask is described. A device layer having a photo-resist layer formed thereon is first provided. The photo-resist layer is patterned to form a photo-resist template mask. A spacer-forming material layer is deposited over the photo-resist template mask. The spacer-forming material layer is etched to form a spacer mask and to expose the photo-resist template mask. The photo-resist template mask is then removed and an image of the spacer mask is finally transferred to the device layer.04-30-2009
20100022100BI-LAYER CAPPING OF LOW-K DIELECTRIC FILMS - A method is provided for processing a substrate surface by delivering a first gas mixture comprising a first organosilicon compound, a first oxidizing gas, and one or more hydrocarbon compounds into a chamber at deposition conditions sufficient to deposit a first low dielectric constant film on the substrate surface. A second gas mixture having a second organosilicon compound and a second oxidizing gas is delivered into the chamber at deposition conditions sufficient to deposit a second low dielectric constant film on the first low dielectric constant film. The flow rate of the second oxidizing gas into the chamber is increased, and the flow rate of the second organosilicon compound into the chamber is decreased to deposit an oxide rich cap on the second low dielectric constant film.01-28-2010
20100075503INTEGRAL PATTERNING OF LARGE FEATURES ALONG WITH ARRAY USING SPACER MASK PATTERNING PROCESS FLOW - Embodiments of the present invention pertain to methods of forming patterned features on a substrate having an increased density (i.e. reduced pitch) as compared to what is possible using standard photolithography processing techniques using a single high-resolution photomask while also allowing both the width of the patterned features and spacing (trench width) between the patterned features to vary within an integrated circuit.03-25-2010
20100136792SELF-ALIGNED MULTI-PATTERNING FOR ADVANCED CRITICAL DIMENSION CONTACTS - Embodiments of the present invention pertain to methods of forming patterned features on a substrate having a reduced pitch in two dimensions as compared to what is possible using standard photolithography processing techniques using a single high-resolution photomask. A spacer layer is formed over a two-dimensional square grid of cores with a thickness chosen to leave a dimple at the center of four cores on the corners of a square. The spacer layer is etched back to reveal the substrate at the centers of the square. Removing the core material results in double the pattern density of the lithographically defined grid of cores. The regions of exposed substrate may be filled again with core material and the process repeated to quadruple the pattern density.06-03-2010

Patent applications by Christopher Dennis Bencher, San Jose, CA US

Christopher Dennis Bencher, Sunnyvale, CA US

Patent application numberDescriptionPublished
20090050902SEMICONDUCTOR DEVICE HAVING SILICON CARBIDE AND CONDUCTIVE PATHWAY INTERFACE - The present invention provides semiconductor device formed by an in situ plasma reducing process to reduce oxides or other contaminants, using a compound of nitrogen and hydrogen, typically ammonia, at relatively low temperatures prior to depositing a subsequent layer thereon. The adhesion characteristics of the layers are improved and oxygen presence is reduced compared to the typical physical sputter cleaning process of an oxide layer. This process may be particularly useful for the complex requirements of a dual damascene structure, especially with copper applications.02-26-2009

Patent applications by Christopher Dennis Bencher, Sunnyvale, CA US