Patent application number | Description | Published |
20120074982 | DEVICE FOR MONITORING THE OPERATION OF A DIGITAL CIRCUIT - A digital electronic circuit includes: a plurality of sequential elements; at least one data-conducting path connecting an input sequential element to a destination sequential element; a clock outputting a clock signal on a clock tree for setting the speed of the sequential elements; a monitoring device receiving, as an input, at least one data signal traveling on a conducting path and arriving at a destination sequential element, the monitoring device including: a module for defining at least one detection window according to the clock tree; and a detector for detecting a transition of each data signal received during a detection window; and wherein each detection window is defined so as to enable the detection or anticipation of a fault corresponding to a violation of the rise time or the maintenance time of a data signal relative to a clock signal edge received by the destination sequential element receiving the data signal. | 03-29-2012 |
20120131242 | Method and Device for Asynchronous Communication of Data on a Single Conductor - The invention relates to the asynchronous communication of data in complex integrated systems, be it inside integrated circuit chips or between integrated circuit chips, for example in a compact stack of chips. According to the invention, the transmission is done on a single conductor of exchanges. The data are transmitted on this conductor in the form of at least three levels of potential, the first level representing a first value of data item transmitted, the second representing a second value of data item transmitted, and the third representing an inactive level. An acknowledgment signal is transmitted on the same exchange conductor as the data. This signal is preferably sent by the receiver in the form of the forcing of the exchange conductor by the receiver to the inactive potential level, the sender detecting this forcing. | 05-24-2012 |
20130262358 | ELECTRONIC CIRCUIT WITH NEUROMORPHIC ARCHITECTURE - Neuromorphic circuits are multi-cell networks configured to imitate the behavior of biological neural networks. A neuromorphic circuit is provided which comprises a network of neurons each identified by a neuron address in the network, each neuron being able to receive and process at least one input signal and then later emit on an output of the neuron a signal representing an event which occurs inside the neuron, and a programmable memory composed of elementary memories each associated with a respective neuron. The elementary memory, which is a memory of post-synaptic addresses and weights, comprises an activation input linked by a conductor to the output of the associated neuron to directly receive an event signal emitted by this neuron without passing through an address encoder or decoder. The post-synaptic addresses extracted from an elementary memory activated by a neuron are applied, with associated synaptic weights, as inputs to the neural network. | 10-03-2013 |
20130321057 | INTEGRATED CIRCUIT COMPRISING AT LEAST ONE DIGITAL OUTPUT PORT HAVING AN ADJUSTABLE IMPEDANCE, AND CORRESPONDING ADJUSTMENT METHOD - An integrated circuit may include a digital output port including a buffer stage that includes subassemblies of MOSFET transistors. One subassembly may include two pull-up transistors having sources connected to a common high voltage, and having drains connected to a common node connected to the output terminal. Another subassembly may include pull-down transistors having sources connected to a common low voltage, and having drains connected to the common node. The pull-up and pull-down transistors are formed in a thin semiconductor layer of an FDSOI substrate. The substrate may include a thick semiconductor layer and an oxide layer separating the thin and thick semiconductor layers. Areas of the thick semiconductor layer facing the pull-up and pull-down transistors may be connected to a circuit configured to vary a threshold voltage of the pull-up and pull-down transistors. | 12-05-2013 |
20150048864 | LOW CONSUMPTION LOGIC CIRCUIT WITH MECHANICAL SWITCHES - Adiabatic logic circuit having a first and a second inputs, a first and a second outputs and at least one supply and synchronisation input (Phi), with this circuit comprising:
| 02-19-2015 |
Patent application number | Description | Published |
20090045287 | AIRCRAFT WITH REDUCED ENVIRONMENTAL IMPACT - Aircraft with reduced environmental impact. | 02-19-2009 |
20100032518 | AIRCRAFT FUSELAGE - An aircraft fuselage including a front part including a cockpit, a central part, and a rear part. The central part of the fuselage includes a first zone located at the front part and that increases in width to a maximum width towards the rear of the aircraft, a second zone that decreases in width, and a third zone that has an essentially constant width and is located behind the second zone, width begin measured along the pitch axis. | 02-11-2010 |
20100170981 | ENERGY STORAGE AERODYNAMIC BRAKING DEVICE AND METHOD - In order to generate an efficient aerodynamic braking force, whatever the speed of a vehicle such as an airplane flying in the air, the method includes a step for the production of energy by the vehicle, a step of storage of the energy produced and a step of utilisation of such energy to drive a propeller which generates a force opposing the forward motion of the vehicle. Energy is produced by using the displacement of the vehicle with respect to air using a propeller driving a generator, or using the displacement with respect to the ground, using wheels driving a generator, or using generators driven by motors of the vehicle. The energy can be stored in the pneumatic, electric or kinetic form and the generation and driving means are selected according to the technology used for the storage means. | 07-08-2010 |
Patent application number | Description | Published |
20080258270 | Mgo-Based Coating for Electrically Insulating Semiconductive Substrates and Production Method Thereof - The present invention relates to a magnesium oxide-based (MgO) inorganic coating intended to electrically insulate semiconductive substrates such as silicon carbide (SiC), and to a method for producing such an insulating coating. The method of the invention comprises the steps of preparing a treatment solution of at least one hydrolysable organomagnesium compound and/or of at least one hydrolysable magnesium salt, capable of forming a homogeneous polymer layer of magnesium oxyhydroxide by hydrolysis/condensation reaction with water; depositing the treatment solution of the hydrolysable organomagnesium compound or of the hydrolysable magnesium salt, onto a surface to form a magnesium oxide-based layer; and densifying the layer formed at a temperature of less than or equal to 1000° C. | 10-23-2008 |
20080292790 | Process For Producing a Coating Based on an Oxide Ceramic that Conforms to the Geometry of a Substrate Having Features in Relief - The invention relates to a process for producing layers made of oxide ceramic that conform to substrates having features in relief comprising:
| 11-27-2008 |
20090241496 | Process for Producing a Nanoporous Layer of Nanoparticles and Layer Thus Obtained - Process for producing at least one nanoporous layer of nanoparticles chosen from nanoparticles of a metal oxide, nanoparticles of metal oxides, and mixtures of said nanoparticles, on a surface of a substrate, in which at least one colloidal sol, in which said nanoparticles are dispersed and stabilized, is injected into a thermal plasma jet which sprays said nanoparticles onto said surface. | 10-01-2009 |
20110003130 | ORGANIC-INORGANIC HYBRID MATERIAL, OPTICAL THIN LAYER OF THIS MATERIAL, OPTICAL MATERIAL COMPRISING SAME, AND PROCESS FOR PRODUCING SAME - Organic-inorganic composite material comprising:
| 01-06-2011 |
20130260283 | ORGANIC-INORGANIC HYBRID NANOFIBRES HAVING A MESOPOROUS INORGANIC PHASE, PREPARATION THEREOF BY ELECTROSPINNING, MEMBRANE, ELECTRODE, AND FUEL CELL - Organic-inorganic hybrid nanofibres comprising two phases:
| 10-03-2013 |
20140037839 | PREPARATION OF STABLE METAL OXIDE SOLS, NOTABLY FOR MAKING THIN ABRASION-RESISTANT FILMS WITH OPTICAL PROPERTIES - The invention relates to a method for preparing sols of metal oxides, with an aqueous component, which are stable over time and which notably allow the making of thin films having both remarkable optical and abrasion resistance properties. | 02-06-2014 |
20140332935 | MgO-Based Coating for Electrically Insulating Semiconductive Substrates and Production Method Thereof - The present invention relates to a magnesium oxide-based (MgO) inorganic coating intended to electrically insulate semiconductive substrates such as silicon carbide (SiC), and to a method for producing such an insulating coating. The method of the invention comprises the steps of preparing a treatment solution of at least one hydrolysable organomagnesium compound and/or of at least one hydrolysable magnesium salt, capable of forming a homogeneous polymer layer of magnesium oxyhydroxide by hydrolysis/condensation reaction with water; depositing the treatment solution of the hydrolysable organomagnesium compound or of the hydrolysable magnesium salt, onto a surface to form a magnesium oxide-based layer; and densifying the layer formed at a temperature of less than or equal to 1000° C. | 11-13-2014 |