| Patent application number | Description | Published |
|---|
| 20110057728 | AMPLIFIER CIRCUIT, INTEGRATED CIRCUIT AND RADIO FREQUENCY COMMUNICATION UNIT - An amplifier circuit for amplifying an input signal received at an input node of the amplifier circuit. The amplifier circuit comprises a feedback resistance connected between the input node of the amplifier circuit and an output node of the amplifier circuit. Transconductance circuitry is arranged to inject a transconductance current at a point along the feedback resistance. The transconductance circuitry is configurable to vary the point along the feedback resistance where the transconductance current is injected. | 03-10-2011 |
| 20110065412 | MIXER CIRCUIT, INTEGRATED CIRCUIT DEVICE AND RADIO FREQUENCY COMMUNICATION UNIT - A mixer circuit comprises an input stage arranged to convert an input voltage signal received at an input of the mixer circuit into at least one current signal, and a frequency conversion stage comprising at least one switching element arranged to convert a signal component of the at least one current signal from an input frequency to a output frequency. The input stage comprises at least one resistance connected between the input of the mixer circuit and the at least one switching element. The at least one switching element and the at least one resistance are arranged such that the at least one switching element comprises a ‘turn-on’ resistance that exhibits a resistivity that is a factor less than the at least one resistance connected thereto. | 03-17-2011 |
| 20110109389 | AMPLIFIER CIRCUIT, INTEGRATED CIRCUIT AND RADIO FREQUENCY COMMUNICATION UNIT - An amplifier circuit for amplifying a differential input signal includes a first feedback resistance, a second feedback resistance, first transconductance circuitry, and second transconductance circuitry. The first feedback resistance is connected between a first input node and a first output node of the amplifier circuit. The second feedback resistance is connected between a second input node and a second output node of the amplifier circuit. The first transconductance circuitry is arranged to inject a transconductance current at a point along the first feedback resistance, and is configurable to vary the point along the first feedback resistance where the transconductance current is injected. The second transconductance circuitry is arranged to inject another transconductance current at a point along the second feedback resistance, and is configurable to vary the point along the second feedback resistance where the another transconductance current is injected. | 05-12-2011 |
| Patent application number | Description | Published |
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| 20090038997 | METHOD FOR SORTING INTEGRATED CIRCUIT DEVICES - A method for sorting integrated circuit (IC) devices of the type having a substantially unique identification (ID) code, such as a fuse ID, including automatically reading the ID code of each of the IC devices and sorting the IC devices in accordance with their automatically read ID codes, is disclosed. | 02-12-2009 |
| 20090060703 | METHOD FOR SORTING INTEGRATED CIRCUIT DEVICES - A method for sorting integrated circuit (IC) devices of the type having a substantially unique identification (ID) code, such as a fuse ID, including automatically reading the ID code of each of the IC devices and sorting the IC devices in accordance with their automatically read ID codes, is disclosed. | 03-05-2009 |
| 20090245009 | 256 Meg dynamic random access memory - A 256 Meg dynamic random access memory is comprised of a plurality of cells organized into individual arrays, with the arrays being organized into 32 Meg array blocks, which are organized into 64 Meg quadrants. Sense amplifiers are positioned between adjacent rows in the individual arrays while row decoders are positioned between adjacent columns in the individual arrays. In certain of the gap cells, multiplexers are provided to transfer signals from I/O lines to datalines. A data path is provided which, in addition to the foregoing, includes array I/O blocks, responsive to the datalines from each quadrant to output data to a data read mux, data buffers, and data driver pads. The write data path includes a data in buffer and data write muxes for providing data to the array I/O blocks. A power bus is provided which minimizes routing of externally supplied voltages, completely rings each of the array blocks, and provides gridded power distribution within each of the array blocks. A plurality of voltage supplies provide the voltages needed in the array and in the peripheral circuits. The power supplies are organized to match their power output to the power demand and to maintain a desired ratio of power production capability and decoupling capacitance. A powerup sequence circuit is provided to control the powerup of the chip. Redundant rows and columns are provided as is the circuitry necessary to logically replace defective rows and columns with operational rows and columns. Circuitry is also provided on chip to support various types of test modes. | 10-01-2009 |
| 20090273360 | SYSTEM FOR ISOLATING A SHORT-CIRCUITED INTEGRATED CIRCUIT (IC) FROM OTHER ICs ON A SEMICONDUCTOR WAFER - A circuit for isolating a short-circuited integrated circuit (IC) formed on the surface of a semiconductor wafer from other ICs formed on the wafer that are interconnected with the short-circuited IC includes control circuitry within the short-circuited IC for sensing the short circuit. The control circuitry may sense the short circuit in a variety of ways, including sensing excessive current drawn by the short-circuited IC, and sensing an abnormally low or high voltage within the short-circuited IC. Switching circuitry also within the short-circuited IC selectively isolates the short-circuited IC from the other ICs on the wafer in response to the control circuitry sensing the short circuit. As a result, if the wafer is under probe test, for example, testing can continue uninterrupted on the other ICs while the short-circuited IC is isolated. | 11-05-2009 |
| 20110089088 | METHOD FOR SORTING INTEGRATED CIRCUIT DEVICES - A method for sorting integrated circuit (IC) devices of the type having a substantially unique identification (ID) code, such as a fuse ID, including automatically reading the ID code of each of the IC devices and sorting the IC devices in accordance with their automatically read ID codes, is disclosed. | 04-21-2011 |
