| Patent application number | Description | Published |
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| 20080207644 | Therapeutic materials and methods - Disclosed are methods for treating various cancers. Methods encompass the administration of an mTOR inhibitor in combination with a second drug selected from an ImiD, a PDE4 inhibitor, a p38 MAP kinase inhibitor, a xanthine anticytokine, a dual TACE/MMP inhibitor and a proteasome inhibitor. | 08-28-2008 |
| 20090215812 | BIOMARKERS FOR EVALUATING LIKELIHOOD OF TUMOR SENSITIVITY TO AN MTOR INHIBITOR - The present invention provides compositions and methods for evaluating the likelihood that a tumor is sensitive to an mTOR inhibitor, e.g., rapamycin or a rapamycin analog. The invention provides FKBP proteins as biomarkers for predicting the likelihood that a tumor is sensitive to an mTOR inhibitor. The methods include assessing the expression or activity of an FKBP protein, e.g., FKBP 12, in a subject with a tumor or in a sample derived from a tumor. Additional biomarkers and biomarker combinations are also provided. The invention also provides kits containing, e.g., a validated antibody or ligand for assessing the expression or activity of an FKBP protein. | 08-27-2009 |
| 20090311249 | Capecitabine Combination Therapy - The invention provides the use of a combination of an mTOR inhibitor and capecitabine in the treatment of cancer. | 12-17-2009 |
| 20100266590 | COMBINATION THERAPY - Disclosed are methods for treating various cancers. Methods encompass the administration of a first drug such as AP23573, temsirolimus or everolimus in combination with a second drug selected from Remicade, Humira, Enbrel, Raptiva, Abatacept, Actermra, Cimzia or anakinra. | 10-21-2010 |
| Patent application number | Description | Published |
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| 20080219175 | Connectionless configurations for stress testing timing and synchronization in data packet networks - A method and system for providing connectionless configurations for stress testing timing and synchronization in data packet networks. Packet traffic of interest is transmitted through multiple interconnected switching nodes such that different packets can be transmitted over different paths through the switching nodes. The nodes can support background traffic in order to generate delays for the packets at each of the switching nodes. By allowing packets to use multiple paths in a single testing configuration, a connectionless packet flow can be utilized for adaptive packet timing recovery stress testing. | 09-11-2008 |
| 20080219180 | Derivative packet delay variation as a metric for packet timing recovery stress testing - A method and system for analyzing simulated packet delay variation (PDV) using derivative PDV is disclosed. The delay-step method for simulating PDV determines a delay for each packet in a stream of packets generated at a regular interval. Delay target values are randomly selected based on a statistical distribution, such as a Gaussian distribution. Delay-steps are determined for each packet based on the delay target values. The delay-steps can be fixed or variable sized steps which are used to adjust the delay of sequential packets. PDV is generated by delaying each of the packets with the delay determined for that packet. The derivative PDV is calculated to evaluate a delay rate of change on a packet-by-packet basis. The derivative PDV can be used as a metric to specify stresses for adaptive packet timing recovery stress testing. | 09-11-2008 |
| 20080225746 | Method and system for generating packet delay variation with a uniform distribution - A method and system for generating packet delay variation (PDV) with a uniformly distributed probability density function (PDF) for packet timing recovery stress testing. A delay-step method determines a delay for each packet in a stream of packets generated at a regular interval. In the delay-step method, delay-steps are determined for each packet based on delay target values. In order to generate PDV with a uniform PDF, the delay target values are randomly selected based on a pre-biased PDF which is a uniform distribution that is pre-biased by a pre-bias function. The pre-bias function increase the values of small delay target values so that an increased number of delay target values are at the extremes of the uniform distribution. This causes the delay-step method to result in PDV with a uniform distribution. | 09-18-2008 |
| 20080225747 | Simulating packet delay variation using step-target delay method - A method and system for simulating packet delay variation (PDV) is disclosed. The delay-step method for simulating PDV determines a delay for each packet is a stream of packets generated at a regular interval. Delay target values are randomly selected based on a statistical distribution, such as a Gamma distribution, which models a desired PDV. Delay-steps are determined for each packet based on the delay target values. The delay-steps can be fixed or variable sized steps which are used to adjust the delay of sequential packets. Each of the packets is then transmitted with the delay determined for that packet. | 09-18-2008 |
| 20090259445 | Method and apparatus for simulating packet delay variation of a multi-switch network - A packet delay variation simulation system has a packet generator, a packet delay variation generator, and a packet delay analyzer to analyze delayed packets. The packet delay variation generator has multiple delay distribution modules that use both a deterministic delay process and a statistical delay process packet for determining a packet's delay. The packet delay variation generator may utilize different probability density functions to describe various portions of measured packet data. That is, measured packet delay information is analyzed and information from this analysis is used to construct a total delay model for a network. The delay may include a pre-determined deterministic delay offset as well as one or more variable statistical delay offsets. | 10-15-2009 |
| Patent application number | Description | Published |
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| 20080310447 | Methods and Apparatus for Testing Adaptive Timing Characteristics of Packet-based Timing Protocol - Methods and apparatus for testing adaptive timing characteristics of a packet-based timing protocol are provided. A packet delay variation test sequence is applied to packet-based traffic as the packet-based traffic passes through a packet delay variation generator during transmission between nodes. Adaptive timing characteristics at a node that receives the packet-based traffic are evaluated in accordance with the packet delay variation test sequence. | 12-18-2008 |
| 20090141725 | LINE-TIMING IN PACKET-BASED NETWORKS - In a packet-based (e.g., Ethernet) network, such as the network of central offices and base stations of a wireless telephone system, a node receives one or more incoming packet-based signals from one or more other nodes of the network and recovers a clock signal from each incoming packet-based signal. The node selects one of the recovered clock signals as the node's reference clock signal. When the node is part of a base station, the node uses the selected clock to generate and transmit one or more outgoing packet-based signals to one or more central offices. The node also uses the selected clock to generate the base station's wireless transmissions. In one implementation, the base stations and central offices are connected by Ethernet facilities. | 06-04-2009 |
| 20110164627 | THREE-STAGE ARCHITECTURE FOR ADAPTIVE CLOCK RECOVERY - An adaptive clock recovery (ACR) system has a first closed-loop control processor (e.g., a first proportional-integral (PI) processor) that processes an input phase signal indicative of jittery packet arrival times to generate a mean phase reference. The input phase signal is compared to the mean phase reference to generate delay-offset values that are indicative of the delay-floor corresponding to the packet arrival times. The mean phase reference and the delay-offset values are used to generate offset-compensated phase values corresponding to the delay-floor. The ACR system also has a second closed-loop control processor (e.g., a second PI processor) that smoothes the offset-compensated phase values to generate an output phase signal that can be used to generate a relatively phase stable recovered clock signal, even during periods of varying network load that adversely affect the uniformity of the packet arrival times. | 07-07-2011 |
| 20110164630 | ADAPTIVE CLOCK RECOVERY WITH STEP-DELAY PRE-COMPENSATION - An adaptive clock recovery (ACR) subsystem processes an input phase signal indicative of jittery packet arrival times to generate a relatively smooth and bounded output phase signal that can be used to generate a relatively stable recovered clock signal. The input phase signal is also processed to detect and measure step-delays corresponding, for example, to path changes in the network routing of the packets. Step-delay pre-compensation is performed, in which the input phase signal is phase-adjusted, upstream of the ACR subsystem, based on the sign and magnitude of each detected step-delay. As a result, the ACR subsystem is substantially oblivious to the existence of such step-delays. | 07-07-2011 |
